HANBit

HFDOM-40LX Series

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HANBit Electronics Co., Ltd

.

REV 1.0 (February, 2003.)

2. INTERFACE BUS TIMING

ACCESS SPCIFICATIONS

IDE MODE I/O ACCESS SPECIFICATIONS

In this True IDE Mode the Flash Disk Module protocol and configuration are disabled and only I/O operations to the

Task File and Data Register are allowed. In this mode no Memory or Attribute Registers are accessible to the host.

Table 3.1 IDE Mode I/O Read Access

Mode

-CE2

-CE1

A2-A0

-IORD

-IOWR

D15 - D8

D7 – D0

Invalid Mode

L

L

x

x

x

High-Z

High-Z

Standby Mode

H

H

x

x

x

High-Z

High-Z

Task File Read

H

L

1-7h

L

H

High-Z

Data Out

Data Register Read

L

H

L

L

H

Odd Byte out

Even Byte out

Table 3.2 IDE Mode I/O Read Timing

Parameter

Symbol

IEEE Symbol

Min. ns

Max. ns

Data Delay after IORD

td (IORD)

tlGLQV

100

Data Hold following IORD

th (IORD)

tlGHQX

0

IORD Width Time

tw (IORD)

tlGLIGH

165

Address Setup before IORD

tsuA (IORD)

tAVIGL

70

Address Hold following IORD

thA (IORD)

tlGHAX

20

CE Setup before IORD

tsuCE (IORD)

tELIGL

5

CE Hold following IORD

thCE (IORD)

tlGHEH

20

IOIS16 Delay Falling from Address

tdfIOIS16 (ADR)

tAVISL

35

IOIS16 Delay Rising from Address

tdrIOIS16 (ADR)

tAVISH

35

NOTE: The maximum load on -IOIS16 is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time

from

–WAIT high to -IORD high is 0nsec, but minimum -IORD width must still be met.