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24LLC16 Datasheet(PDF) 8 Page - Ceramate Technical |
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24LLC16 Datasheet(HTML) 8 Page - Ceramate Technical |
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8 / 22 page ![]() 24LLC16 16K-Bit-Serial EEPROM * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Fax:886-3-3521052 Page 8 of 22 Rev 1.0 Aug.5, 2002 BYTE WRITE OPERATION In a complete byte write operation, the master transmits the slave address, word address, and one data byte to the 24LLC16 slave device (see Figure 5-9). Slave Address Word Address Start A C K A C K Data Stop A C K Figure 5-9. Byte Write Operation Following a start condition, the master sends the device identifier (4 bits), three “don’t care” bits, and an R/W bit set to “0” onto the bus. Then the addressed 24LLC16 generates an ACK, and waits for the next byte. The next byte to be transmitted by the master is the word address. This 8-bit address is written into the word address pointer of the 24LLC16 When the 24LLC16 receives the word address, it responds by issuing an ACK and then waits for the next 8- bit data. When it receives the data byte, the 24LLC16 again responds with an ACK. The master terminates the transfer by generating a Stop condition, at which time the 24LLC16 begins the internal write cycle. While the internal write cycle is in progress, all 24LLC16 inputs are disabled and the 24LLC16 does not respond to any additional request from the master. |
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