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V55C2256164VB Rev. 1.0 April 2005
ProMOS TECHNOLOGIES
V55C2256164VB
1. Bank Activate Command Cycle
(CAS latency = 3)
2. Burst Read Operation
(Burst Length = 4, CAS latency = 2, 3)
ADDRESS
CLK
T0
T
T1
T
TTT
COMMAND
NOP
NOP
NOP
Bank A
Row Addr.
Bank A
Activate
Write A
with Auto
Bank A
Col. Addr.
. . . . . . . . . .
. . . . . . . . . .
. . . . . . . . . .
Bank B
Activate
Bank A
Row Addr.
Bank A
Activate
tRCD
: “H” or “L”
tRC
Precharge
tRRD
Bank B
Row Addr.
COMMAND
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DOUT A0
CAS latency = 2
t
CK3, I/O’s
CAS latency = 3
DOUT A1
DOUT A2
DOUT A3
NOP
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
t
CK2, I/O’s
DOUT A0
DOUT A1
DOUT A2
DOUT A3