ProMOS TECHNOLOGIES
V55C2256164VB
8
V55C2256164VB Rev. 1.0 April 2005
Address Input for Mode Set (Mode Register Operation)
Similar to the page mode of conventional
DRAM’s, burst read or write accesses on any col-
umn address are possible once the RAS cycle
latches the sense amplifiers. The maximum tRAS or
the refresh interval time limits the number of random
column accesses. A new burst access can be done
even before the previous burst ends. The interrupt
operation at every clock cycles is supported. When
the previous burst is interrupted, the remaining ad-
dresses are overridden by the new address with the
full burst length. An interrupt which accompanies
with an operation change from a read to a write is
possible by exploiting DQM to avoid bus contention.
When
two
or
more
banks
are
activated
sequentially,
interleaved
bank
read
or
write
operations are possible. With the programmed
burst length, alternate access and precharge
operations on two or more banks can realize fast
serial data access modes among many different
pages. Once two or more banks are activated,
column to column interleave operation can be done
between different pages.
A12 ...
A3
A4
A2
A1
A0
A7
A6
A5
Address Bus (Ax)
BT
Burst Length
CAS Latency
Mode Register
CAS Latency
A6
A5
A4
Latency
0
0
0
Reserve
00
1
1
01
0
2
01
1
3
1
0
0
Reserve
1
0
1
Reserve
1
1
0
Reserve
1
1
1
Reserve
Burst Length
A2
A1
A0
Length
Sequential
Interleave
000
1
1
001
2
2
010
4
4
011
8
8
1
0
0
Reserve
Reserve
1
0
1
Reserve
Reserve
1
1
0
Reserve
Reserve
1
1
1
Full page
Reserve
Burst Type
A3
Type
0
Sequential
1
Interleave
Operation Mode
BA1 BA0 A12 A11 A10 A9 A8 A7
Mode
00000
0
0
0
Burst Read/Burst
Write
00000
1
0
0
Burst Read/Single
Write
Operation Mode
BA0
BA1
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