AP64501

Document number: DS41980 Rev. 4 - 2

16 of 26

www.diodes.com

August 2019

© Diodes Incorporated

AP64501

Application Information (cont.)

14

Output Capacitor

The output capacitor keeps the output voltage ripple small, ensures feedback loop stability, and reduces both the overshoots and undershoots of

the output voltage during load transients. During the first few microseconds of an increasing load transient, the converter recognizes the change

from steady-state and enters 100% duty cycle to supply more current to the load. However, the inductor limits the change to increasing current

depending on its inductance. Therefore, the output capacitor supplies the difference in current to the load during this time. Likewise, during the first

few microseconds of a decreasing load transient, the converter recognizes the change from steady-state and sets the on-time to minimum to

reduce the current supplied to the load. However, the inductor limits the change in decreasing current as well. Therefore, the output capacitor

absorbs the excess current from the inductor during this time.

The effective output capacitance, COUT, requirements can be calculated from the equations below.

The ESR of the output capacitor dominates the output voltage ripple. The amount of ripple can be calculated by:

(

)

Eq. 10

An output capacitor with large capacitance and low ESR is the best option. For most applications, a 22µF to 68µF ceramic capacitor is sufficient.

To meet the load transient requirements, the calculated COUT should satisfy the following inequality:

(

)

Eq. 11

Where:



ITrans is the load transient



∆VOvershoot is the maximum output overshoot voltage



∆VUndershoot is the maximum output undershoot voltage

15

Bootstrap Capacitor and Low-Dropout (LDO) Operation

To ensure proper operation, a ceramic capacitor must be connected between the BST and SW pins. A 100nF ceramic capacitor is sufficient. If the

bootstrap capacitor voltage falls below 2.3V, the boot undervoltage protection circuit turns Q2 on for 300ns to refresh the bootstrap capacitor and

raise its voltage back above 2.55V. The bootstrap capacitor threshold voltage is always maintained to ensure enough driving capability for Q1.

This operation may arise during long periods of no switching such as in PFM with light load conditions. Another event that requires the refreshing

of the bootstrap capacitor is when the input voltage drops close to the output voltage. Under this condition, the regulator enters low-dropout mode

by holding Q1 on for multiple clock cycles. To prevent the bootstrap capacitor from discharging, Q2 is forced to refresh. The effective duty cycle is

approximately 100% so that it acts as an LDO to maintain the output voltage regulation.