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ISL68229IRAZ Datasheet(PDF) 13 Page - Renesas Technology Corp |
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ISL68229IRAZ Datasheet(HTML) 13 Page - Renesas Technology Corp |
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13 / 107 page ![]() ISL68229, ISL68239 1. Overview R16DS0006EU0101 Rev.1.01 Page 13 of 106 Jul 21, 2022 1.5 Functional Pin Descriptions See Table 4 on page 33 for design layout considerations. ISL68229 Pin Number ISL68239 Pin Number Pin Name Description 6, 5, 4, 3, 2, 1, 68, 67, 66, 65, 64, 63 6, 5, 4, 3, 2, 1, 68, 67, 66, 65, 64, 63 PWM[11:0] Pulse-Width Modulation (PWM) outputs. Connect these pins to the PWM input pins of 3.3V logic-compatible smart power stages, driver ICs, or DrMOS. 7 7 CFP Catastrophic fault protection output. This active, high-logic signal can be configured to alert the host to major fault events. 8 8 nVRHOT Thermal warning indicator. This open-drain output is pulled low in the event of a sensed over-temperature at the TEMP pins. 9, 11 - DNC Do not connect any signals to these pins. 10, 12 - GND Connect to ground - 9 AVS_VDDIO AVSBus reference voltage input. Leave open if not used. - 10 AVS_MDA AVSBus data input pin. Connect to ground if not used. - 11 AVS_SDA AVSBus data output pin. Leave open if not used. - 12 AVS_CLK Synchronous clock signal input of the AVSBus. Connect to ground if not used. 15, 14, 13 15, 14 13 EN[2:0] Input pin used for enable control of outputs. Connect to ground if not used. 18, 17, 16 18, 17, 16 PG[2:0] Open-drain, power-good indicator for outputs. 19 19 VINSEN Input voltage sense pin for the VIN supply voltage. 20, 21 20, 21 DNC Do not connect any signals to these pins. 22 22 VMON Input voltage sense pin for the driver supply voltage. 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45 CSRTN[11:0] The CS and CSRTN pins are current-sense inputs to individual phase differential amplifiers. Unused phases should have their respective current-sense inputs grounded. These pins support smart power stage, DCR, and resistor sensing. Connection details depend on the current-sense method chosen. 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46 CS[11:0] 54, 50, 47 54, 50, 47 RGND[2:0] Negative differential voltage sense input for outputs. Connect to a negative remote sensing point. Connect to ground if not used. 55, 51, 48 55, 51, 48 VSEN[2:0] Positive differential voltage sense input for outputs. Connect to a positive remote sensing point. Connect to ground if not used. 53, 52, 49 53, 52, 49 TEMP[2:0] Input pin for sensing external temperature measurement at outputs. Supports NTC-based temperature sensing and smart power stage sensing. Connect to ground if not used. 56 56 CONFIG Configuration ID selection pin. Attach a resistor from this pin to GND. 57 57 ADDRESS SMBus/PMBus address selection pin. 58 58 VCC Chip primary bias input. Connect this pin directly to a +3.3V supply with a 1µF or greater MLCC bypass capacitor. 59 59 VCCS Internally generated 1.2V LDO logic supply from VCC. Decouple with a 4.7µF or greater MLCC (X5R or better). 60 60 nPMALERT Open-drain output pin for alerting the SMBus host. 61 61 PMSCL Serial clock signal pin for the SMBus interface. 62 62 PMSDA Serial data signal pin for the SMBus interface. EPAD EPAD GND The package pad serves as the GND return for all IC functions. Connect directly to the system GND plane with multiple vias. |
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