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FXPS7400DI4 Datasheet(PDF) 41 Page - NXP Semiconductors |
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FXPS7400DI4 Datasheet(HTML) 41 Page - NXP Semiconductors |
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41 / 75 page ![]() NXP Semiconductors FXPS7400D4 Digital absolute pressure sensor, 20 kPa to 400 kPa Bit 7 6 5 4 3 2 1 0 Symbol WHO_AM_I[7:0] Factory default (stored value) 0 0 0 0 0 0 0 0 Factory default (read value) 1 1 0 0 0 1 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Table 61. WHO_AM_I - device identification register (address 3Eh) bit allocation The default register value is 00h. If the register value is 00h, a value of C4h is transmitted in response to a read command. For all other register values, the actual register value is transmitted in response to a read command. WHO_AM_I register value (hex) Response to a register read command 00h C4h 01h to FFh Actual register value Table 62. WHO_AM_I register values 7.7.10 I2C_ADDRESS - I2C client address register (address 3Fh) The I2C client address register is a user programmed read/write register that contains the unique I2C client address. The register is readable in all modes. This register is included in the read/write array error detection. Bit 7 6 5 4 3 2 1 0 Symbol I2C_ADDRESS[7:0] Factory Default (stored value) 0 0 0 0 0 0 0 0 Factory Default (read value) 0 1 1 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Table 63. I2C_ADDRESS - I2C client address register (address 3Fh) bit allocation The default register value is 00h. If the register value is 00h, the I2C client address is 60h and a value of 60h is transmitted in response to a read command. If the register is written to a value other than 00h, the I2C client address is the lower seven bits of the actual register value and the actual register value is transmitted in response to a read command. 7.7.11 DSP Configuration Registers (DSP_CFG_Ux) The DSP Configuration registers (DSP_CFG_Ux) are a series of registers that affect the DSP data path. There are 4 DSP Configuration registers which are DSP_CFG_U1, DSP_CFG_U3, DSP_CFG_U4, and DSP_CFG_U5. 7.7.11.1 DSP_CFG_U1 - DSP user configuration #1 register (address 40h) The DSP user configuration register #1 is a user programmable read/write register that contains DSP-specific configuration information. This register is included in the read/write array error detection. Changes to this register reset the DSP data path. The contents of the SNSDATA_x registers are not guaranteed until the DSP has completed initialization as specified in Table 105. Reads of the SNSDATA_x registers and sensor data requests should be prevented during this time. FXPS7400D4 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2022. All rights reserved. Product data sheet Rev. 6 — 6 June 2022 41 / 75 |
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