Datasheet

8-Feb-2022

CFR0011-120-01

Revision 1.07

Page 4 of 19

SLGC55544CV

USB Charging Port Power Switch and Controller

©2022 Renesas Electronics Corporation

Electrical Characteristics

Conditions are -40 ≤ TJ ≤ 125 °C unless otherwise noted. VEN = VIN = 5 V, RFAULT# = 10 kΩ, RILIM_L = 80 kΩ, RILIM_H = 20 kΩ,

ILIM_SEL = VIN, CTL1 = CTL2 = CTL3 = VIN, unless otherwise noted. Positive currents are into pins. Typical values are at 25 °C.

All voltages are with respect to GND unless otherwise noted.

Thermal Information 1

Parameter

Typ.

Unit

θ

JA

Junction-to-ambient thermal resistance 2

53.4

°C/W

θ

JCtop

Junction-to-case (top) thermal resistance 3

51.4

°C/W

θ

JB

Junction-to-board thermal resistance 4

17.2

°C/W

ψ

JT

Junction-to-top characterization parameter 5

3.7

°C/W

ψ

JB

Junction-to-board characterization parameter 6

20.7

°C/W

θ

JCbot

Junction-to-case (bottom) thermal resistance 7

3.9

°C/W

Note:

1. For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report,

SPRA953.

2. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K

board, as specified in JESD51-7, in an environment described in JESD51-2a.

3. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific

JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

4. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control

the PCB temperature, as described in JESD51-8.

5. The junction-to-top characterization parameter,

ψ

JT, estimates the junction temperature of a device in a real system and is

extracted from the simulation data for obtaining

θ

JA, using a procedure described in JESD51-2a (sections 6 and 7).

6. The junction-to-board characterization parameter,

ψ

JB, estimates the junction temperature of a device in a real system and is

extracted from the simulation data for obtaining

θ

JA, using a procedure described in JESD51-2a (sections 6 and 7).

7. The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No

specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Electrical Characteristics - Power Switch

Symbol

Parameter

Condition/Note

Min.

Typ.

Max.

Unit

Rds ON

Static drain-source on-state

resistance 1

IOUT = 100 mA,

VILIM_SEL = Logic Low

--

73

--

m

Ω

TA = TJ = 25°C, IOUT = 2 A,

VILIM_SEL = Logic HIgh

--

73

84

m

Ω

-40°C ≤ TA = TJ ≤ 85°C,

IOUT = 2 A, VILIM_SEL = Logic High

--

73

105

m

Ω

-40°C ≤ TA = TJ ≤ 125°C,

IOUT = 2 A, VILIM_SEL = Logic High

--

73

120

m

Ω

TR

Rise Time, Output

CLOAD = 1 µF, RLOAD = 100 Ω

0.7

1.50

1.6

ms

TF

Fall Time, Output

CLOAD = 1 µF, RLOAD = 100 Ω

0.2

0.35

0.5

ms

RDIS

VOUT Discharge

Resistance

337

498

681

Ω

TDIS

Out Discharge Hold Time

--

2

--

s

TDIS_LONG

Long Out Discharge Hold

Time 2

Time VOUT < 0.7 V

1

2

3

s

TDIS_SHORT

Short Out Discharge Hold

Time 2

Time VOUT < 0.7 V

150

250

400

ms

IREV

Reverse Leakage Current

VOUT = 5.5 V, VIN = VEN = 0 V, TJ = 25 °C

--

--

2

µA