XRT72L53 datasheet(21/467 Pages) EXAR

21 / 467 page

XRT72L53

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THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

REV. P1.1.7

PRELIMINARY

F18

TxNIBClk[0]/

SndFCS[0]

Transmit Nibble Clock Output Signal/Transmit HDLC - SEND

FRAME CHECK SEQUENCE Input - Channel 0:

The exact function of this input pin depends upon whether Channel 0

has been configured to operate in the “High-Speed HDLC Controller”

Mode, or not.

Non-High Speed HDLC Controller Mode - Transmit Nibble Clock

output signal - Channel 0:

If the user opts to operate Channel 0 in the “Nibble-Parallel” mode, then

the XRT72L53 Framer IC will derive this clock signal from either the

“TxInClk[0]” or the “RxLineClk[0]” signal (depending upon which signal

is selected as the timing reference).

The user is advised to configure the Terminal Equipment to output the

“outbound” payload data (to the XRT72L53 Framer IC) onto the

“TxNib[3:0][0]” input pins, upon the rising edge of this clock signal.

NOTES:

1. For DS3 applications, the XRT72L53 Framer IC will output 1176

clock edges (to the Terminal Equipment) for each “outbound”

DS3 frame.

2. For E3, ITU-T G.832 applications, the XRT72L53 Framer IC will

output 1074 clock edges (to the Terminal Equipment) for each

“outbound” E3 frame.

3. For E3, ITU-T G.751 applications, the XRT72L53 Framer IC will

output 384 clock edges (fo the Terminal Equipment) for each

“outbound” E3 frame.

High-Speed HDLC Controller Mode - SEND FRAME CHECK

SEQUENCE Input - Channel 0:

The Terminal Equipment is expected to pull this input pin “High” when-

ever the “FCS bytes” are being transmitted, after transmitting a valid

HDLC message.

F19

RxSer[0]/

RxIdle[0]

Receive Serial Output/Receive Flag Sequence Output - Channel 0

The exact function of this output pin depends upon whether Channel 0

is operating in the “High-Speed HDLC Controller” Mode, or not.

Non High Speed HDLC Controller Mode - Channel 0:

If the user opts to operate Channel 0 in the serial mode, then the chip

will output the payload data, of the incoming DS3 or E3 frames, via this

pin. Channel 0 will output this data upon the rising edge of RxClk[0].

The user is advised to design the Terminal Equipment such that it will

sample this data on the falling edge of RxClk[0].

NOTE: This signal is only active if the NibInt input pin is pulled "Low".

High Speed HDLC Controller Mode - Receive Flag Sequence Indi-

cator - Channel 0:

This pin will go high indicating the idle period of sent HDLC data pack-

ets. Also, in combination with ValFCS[0] it can indicate error conditions.

PIN DESCRIPTION CONNECTED PINS

PIN #PIN NAME

TYPE

DESCRIPTION

XRT72L53 Datasheet(PDF) 21 Page - Exar Corporation

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