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Table 1 PC87782 Signals (100-Pin Package)

Signal Name

Type

Function

32KCLKIN

Input

32.768 KHz Oscillator Clock Input

32KX2

Oscillator

32.768 KHz Crystal Oscillator Interface

AMP0

Analog In

Negative Voltage to Port I0 A/D op-amp

AMP1

Analog In

Negative Voltage to Port I1 A/D op-amp

CLK

Output

CPU Clock Output

COL

Input

MII Interface: Collision Detect

CRS

Input

MII Interface: Carrier Sense

DAOUT

Analog Out

D/A Converter Output

ENV0-1

Input

Environment select strap inputs

FAN1

Input

Fan Speed Timer Input 1

FAN2

Input

Fan Speed Timer Input 2

FAN3

Input

Fan Speed Timer Input 3

HA

Input

Host Address line: Distinguishes Commands from Data bytes.

HCSA

Input

Chip Select for Host Interface A

HCSB

Input

Chip Select for Host Interface B

HD0-7

I/O

Bidirectional Data bus used to interface the PC87782 to the peripheral data bus

of a host.

EXHFCLK

Input

For factory test purposes only. Must be pulled permanently high in end

applications.

HIOR

Input

Host I/O Read. Active-low input to signal data read by the host processor.

HIOW

Input

Host I/O Write signal which enables a write operation to the PC87782 through

HD0-7.

HMR

Input

Host Master Reset. Indicates state of Host system.

HPWRON

Input

Host Power On Indication.

IN0-1

Output

LAN Receiver Buffer Management: IN pointer

IRQA

Output

Interrupt A. Signals an interrupt on host channel A.

IRQB

Output

Interrupt B. Signals an interrupt on host channel B.

LOSTPKT

Output

LAN Receiver: Buffer Overflow

MAC_ISOL

Output

Isolates MII from standard LAN MAC when low.

NANDEN

Input

NAND Test Enable / ISE TRI-STATE Control

NTEST

Output

NAND Test Output

OUT0-1

Output

LAN Receiver Buffer Management: OUT pointer

PB0-7

I/O

Port B, bits 0 through 7

PC0-7

I/O

Port C, bits 0 through 7

PF0-7

I/O

Port F, bits 0 through 7

PFAIL

Input

Power Fail (Non-Maskable Interrupt) Input

PI0-7

Analog I/O

Port I A/D converter Analog Inputs. PI0 and PI1 can be configured as analog

feedback outputs for inputs AMP0 and AMP1, respectively.

PL0-7

!/O

General-purpose Wake-Up inputs for RING, CHASSIS, SWIN, BTI and other

events.

RESET

Input

Master Reset to PC87782 device

RXD0-3

Input

MII Interface: Received Data nibble

RX_CLK

Input

MII Interface: Receiver Clock

RX_DV

Input

MII Interface: Receiver Data Valid

RX_ER

Input

MII Interface: Received Error