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PC87782 Datasheet(PDF) 10 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # PC87782
Description  CompactRISC Intelligent System Management Controller
PDF  17 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC87782 Datasheet(HTML) 10 Page - National Semiconductor (TI)

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OSCOUT
Oscillator Output [not characterized]
Analog in
A/D Analog Input signal
Analog out
D/A Analog output signal
Analog I/O
A/D Analog input/output signal
Analog FB
A/D Op-Amp Feedback
MII In
VIH VIL (TTL)
VTRH VTRL
Ethernet IEEE 802.3u compliant input
MII Out
VOHm VOLm
Ethernet IEEE 802.3u compliant output
Table 3 Input Pins
Signal
Type
Pin Number
No. of
Sig Pins
Function
100-pin
160-pin
32KCLKIN
TTL
1
32.768 KHz Oscillator Clock Input.
AMP(1,0)
Analog In
2
Analog Inputs to Op-Amps
ENV(1,0)
STRAP
2
Environment select strap pins. These pins define the
device environment. They are sampled on all resets
except HMR. ENV2 is permanently high in the 100-pin
package.
ENV2
STRAP
N/A
1
HA
TTL
1
Host Address line used in conjunction with the chip-
select inputs to address registers on the Host Interface.
HIOR
TTL
1
Host I/O Read. Active-low input that signals an I/O data
read by the host processor.
HIOW
TTL
1
Host I/O Write. Active-low input that signals an I/O data
write by the host processor.
HCSA
TTL
1
Host Chip Select A. Active-low input that indicates an
access to Channel A by the host processor.
HCSB
TTL
1
Host Chip Select B. Active-low input that indicates an
access to Channel B by the host processor.
HMR
Schmitt
1
Host Master Reset
HPWRON
Schmitt
1
Host Power On. Indicates that the host power supply is
on, and the host bus interface signals are valid. While
HPWRON is low, the host inputs are ignored, and all
outputs float.
NANDEN
Schmitt
1
NAND Test Mode / ISE TRI-STATE Mode
PFAIL
Schmitt
1
Power Fail Detected Input
RESET
Schmitt
1
Master Reset. A low level resets the controller and
inhibits HFCG frequency locking.
RXD0-3
MII In
4
MII Input data.
RX_CLK
MII In
1
MII Receive Clock
RX_DV
MII In
1
MII Receive Data Valid
RX_ER
MII In
1
MII Receive Error
COL
MII In
1
MII Collision Detect
CRS
MII In
1
MII Carrier Sense
TX_CLK
MII In
1
Transmit Clock Input
ISE
Schmitt
N/A
1
ISE Interrupt. reserved for use by the development
system.
Table 2 Pin Descriptions
Signal Type
Input
Parameters
Output
Parameters
Buffer Description



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