Data Sheet

ADG6412

THEORY OF OPERATIONS

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Rev. 0 | 16 of 18

SWITCH ARCHITECTURE

The ADG6412 contains four independent SPST, N-channel diffused

metal-oxide semiconductor (NDMOS) switches, which allows for an

excellent RON performance. Using an NDMOS only architecture re-

sults in a reduction of signal headroom, meaning signals are limited

to VDD – 2 V. To achieve the lowest on resistance, on-resistance

flatness, and total harmonic distortion, it is recommended the signal

stays below VDD – 3.5 V.

To guarantee correct operation of the ADG6412, a minimum of 0.1

µF decoupling capacitors are required on both the VDD and VSS

supply pins.

The ADG6412 is compatible with single-supply systems that have a

VDD of up to 40 V, dual-supply systems of up to ± 22 V, as well as

asymmetric power supplies.

1.8 V LOGIC COMPATIBILITY

For ease of use, the ADG6412 does not have a VL logic reference

voltage. The digital inputs are compatible with 1.8 V logic levels

over the full-operating supply range. The limits for 1.8 V logic are:

VINH = 1.3 V, VINL = 0.8 V. 1.8 V logic-level inputs enable the

ADG6412 to be compatible with processors that have lower supply

rails, eliminating the need for an external voltage translator.

If full 1.8 V and 1.2 V JEDEC compliance is required, refer to

the Analog Devices, Inc., L range part numbers, such as the

ADG1412L.