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74ALS112 Datasheet(PDF) 5 Page - NXP Semiconductors |
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74ALS112 Datasheet(HTML) 5 Page - NXP Semiconductors |
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5 / 10 page ![]() Philips Semiconductors Product specification 74ALS112A Dual J-K negative edge-triggered flip-flop 1996 Jun 27 5 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω UNIT MIN MAX fMAX Maximum clock frequency Waveform 1 35 MHz tPLH tPHL Propagation delay CPn to Qn or Qn Waveform 1 2.0 4.0 10.0 10.5 ns tPLH tPHL Propagation delay SDn or RD to Qn or Qn Waveform 2, 3 1.5 3.5 8.0 9.5 ns AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω UNIT MIN MAX tsu (H) tsu (L) Setup time, High or Low Jn, Kn to CPn Waveform 1 8.0 8.0 ns th (H) th (L) Hold time, High or Low Jn, Kn to CPn Waveform 1 0.0 0.0 ns tw (H) tw (L) CPn Pulse width high or Low Waveform 1 11.0 8.0 ns tw (L) SDn or RDn Pulse width Low Waveform 2, 3 6.0 ns tREC Recovery time, SDn or RDn to CPn Waveform 2, 3 8.0 ns |
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