Philips Semiconductors

Product specification

74ALS273

Octal D-type flip-flop

2

1991 Feb 08

853–1398 01670

FEATURES

DESCRIPTION

The 74ALS273 has eight edge-triggered D-type flip-flops with

individual D inputs and Q outputs. The common buffered clock (CP)

and master reset (MR) inputs load and reset all flip-flops

simultaneously.

The register is fully edge-triggered. The state of each D input, one

setup time before the Low-to-High clock transition, is transferred to

the corresponding flip-flop’s Q output.

All outputs will be forced Low independently of clock or data inputs

by a Low voltage level on the MR input.

The device is useful for applications where the true output only is

required and the CP and MR are common to all flip-flops.

TYPE

TYPICAL

SUPPLY CURRENT

(TOTAL)

74ALS273

95MHz

16mA

PIN CONFIGURATION

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

MR

Q0

D0

D1

Q1

Q2

D2

D3

Q3

Q4

GND

D4

D5

Q5

Q6

D6

D7

Q7

CP

SF00346

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

COMMERCIAL RANGE

DRAWING

NUMBER

20-pin plastic DIP

74ALS273N

SOT146-1

20-pin plastic SO

74ALS273D

SOT163-1

20-pin plastic SSOP

Type II

74ALS273DB

SOT339-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74ALS (U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

D0 – D7

Data inputs

1.0/2.0

20

µA/0.2mA

CP

Clock pulse input (active rising edge)

1.0/1.0

20

µA/0.1mA

MR

Master Reset input (active-Low)

1.0/1.0

20

µA/0.1mA

Q0 – Q7

3-State outputs

130/240

2.6mA/24mA

NOTE:

One (1.0) ALS unit load is defined as: 20

µA in the High state and 0.1mA in the Low state.

LOGIC SYMBOL

3

4

7

8

13

14

18

17

D0

D1

D2

D3

D4

D5

D6

D7

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

2

5

6

9

12

15

16

19

1

11

MR

CP

GND = Pin 10

SF00347

IEC/IEEE SYMBOL

SF00348

1

32

4

5

7

6

8

9

R

11

C1

13

12

14

15

17

16

18

19

1D