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LT3154AVPBF Datasheet(PDF) 16 Page - Analog Devices

Part # LT3154AVPBF
Description  6A Low Noise, High Performance Buck-Boost DC/DC Converter
PDF  32 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LT3154AVPBF Datasheet(HTML) 16 Page - Analog Devices

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LT3154
16
Rev. 0
For more information www.analog.com
OPERATION
In buck mode, the output current is approximately equal
to the inductor current IL:
IOUT(BUCK)≈ IL
In boost mode, the output current is related to average
inductor current and duty cycle by:
IOUT(BOOST)≈ IL • (1‑D)
where D is the converter duty cycle
Since the output current in boost mode is reduced by the
duty cycle (D), the output current rating in buck mode
is always greater than in boost mode. Also, because
boost mode operation requires a higher inductor current
for a given output current compared to buck mode, the
efficiency in boost mode will be lower due to higher con‑
duction (IL² × RDS(ON)) losses in the power switches. This
will further reduce the output current capability in boost
mode. In either operating mode, however, the inductor
peak‑to‑peak ripple current does not play a major role
in determining the output current capability, unlike peak
current mode control.
The maximum output current capability in PWM mode
curves in the Typical Performance Characteristics section
show the relationship of input voltage and the ability to
deliver load current at VOUT = 3.3V. If VOUT drops below
approximately 1V, the inductor current will be reduced
by approximately 50% to limit power dissipation during
a short circuit.
Peak, Reverse and Zero Current Comparators
Theinternalcurrentsensewaveformsareusedbythe Peak
(IPEAK), Reverse (IREVERSE) and Zero current (IZERO) com‑
parators. The IPEAK current comparator monitors ISENSE
and interrupts normal PWM operation if the inductor
current level exceeds its maximum internal threshold.
This threshold is approximately 33% above the maxi‑
mum average current level of the current control loop or
9.5 Amps. If the internal current sense waveform rises
above this level, the LT3154 will disconnect the inductor
from VIN by shutting off switch A to prevent higher current
in the inductor. The IPEAK circuitry is reset by the oscillator
clock at the end of each switching cycle. In the event that
the IPEAK comparator is tripped as the result of an output
short circuit condition, where VOUT is discharged below
approximately 1V, the LT3154 will initiate a soft‑start
event keeping the on‑chip power dissipation to low levels.
Once the short circuit is removed, the LT3154 will restart
in the normal fashion. If the average current loop is able
to prevent inductor current from reaching IPEAK during a
short circuit event, soft‑start will not be initiated, but the
maximum current capability of the current loop will be
reduced by 50% to reduce power dissipation.
In addition to controlling the maximum inductor current,
the LT3154 contains sense circuitry on the D switch to
limit the reverse current as well. The amount of reverse
current allowed depends on the mode of operation. In
PWM mode (SYNC/MODE = 1), the typical reverse cur‑
rent limit is –1.2A, providing clean, fixed frequency switch
operation at light loads and during load step transients.
In BURST mode (SYNC/MODE = 0), the LT3154 operates
withatraditionalzerocurrentcomparator,maintaininghigh
efficiency at light loads and during burst packet intervals.
Once IREVERSE or IZERO is detected, the D switch is shut
off for the remainder of the switching cycle and reset by
the oscillator clock at the end of the cycle.
Oscillator
The frequency of operation is programmed by an external
resistor from the RT pin to ground, according to the fol‑
lowing equation:
RT(kΩ)=
110
fSW MHz
(
)
Therecommendedfrequencyrangeisbetween400kHzand
4MHz, allowing efficiency and external component sizes
to be optimized for each application. An internal 2.2MHz
oscillator frequency can be selected by connecting RT to
VIN, eliminating the need for an external RT resistor. The
LT3154 can also be synchronized to an external clock
source using the SYNC/MODE pin and an internal phase
lock loop (PLL). If synchronization to an external source
is desired, the value of the RT resistor should be chosen
at a frequency 25% to 50% below the applied clock signal
for proper operation.



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