LT3154AVPBF datasheet(23/32 Pages) AD

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LT3154

Rev. 0

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APPLICATIONS INFORMATION

Compensation Example

This section will demonstrate how to derive and select the

compensationcomponentsforatypicalLT3154application.

Designingcompensationforotherapplicationsisamatterof

substitutingdifferentvaluesintheequationsprovidedbased

on the power stage Bode plots. Since the compensation

design procedure uses the simplified model of Figure 5,

theresultsfromthefollowingcompensationdesignshould

alwaysbeverifiedwithtimedomainsteploadresponsetests

to validate the effectiveness of the compensation design. It

is assumed that the value and type of output capacitor will

be selected based on the guidelines provided elsewhere in

this data sheet. Particular attention needs to be paid to the

voltage bias effect on ceramic capacitors typically used for

output bypassing. Similarly, it is assumed that the inductor

value and current rating have been selected as well based

on the application requirements.

Example Application Details:

VIN = 1.8V to 5.5V

VOUT = 3.3V

Maximum IOUT = 1.65A, RLOAD = 2Ω

COUT = 100µF (Use 3x47μF due to DC Bias)

L = 1µH

Since this application includes boost mode operation, the

first step is to calculate the worst case RHPZ frequency

as this will dictate the maximum loop bandwidth for the

converter.

fRHPZ =

VIN2 •RLOAD

VOUT2 •2π•L

(1.8V)2 •2Ω

(3.3V)2 •2π •1µH

= 95kHz

In order to account for internal IC component variations, it

is good practice to set the converter bandwidth or cross‑

over frequency, FCC, at least 5 times lower than the RHPZ

frequency to avoid excessive phase loss from the RHPZ

when operating in boost mode. In this example design,

we’ll plan to achieve a loop bandwidth (FCC) of 20kHz,

FREQUENCY (Hz)

–40

–20

–180

–90

180

100

100000 1000000

1000

3154 F07

10000

PHASE MARGIN

TOTAL GAIN

VEA GAIN

POWER STAGE GAIN

FREQUENCY (Hz)

–40

–20

–180

–90

180

100

100000 1000000

1000

3154 F08

10000

PHASE MARGIN

TOTAL GAIN

VEA GAIN

POWER STAGE GAIN

Figure 6. Buck Bode Plots (VIN > VOUT,

VOUT = 3.3V): Power Stage Gain, VEA Loop Gain,

Total Loop Gain and Phase Margin vs Frequency

Figure 7. Boost Bode Plots (VIN = 1.8V,

VOUT = 3.3V): Power Stage Gain, VEA Loop Gain,

Total Loop Gain and Phase Margin vs Frequency

well below the RHPZ frequency. The 3.3V, 1.65A design

example Bode plots are shown in Figure 6 and Figure 7.

The DC power stage gain in buck mode is simply the

current loop transconductance (10A/V) multiplied by the

load resistance (2Ω). The VOUT resistor divider will be ac‑

counted for in voltage error amplifier (VEA gain) network:

Buck DC Gain 20Log 10A •2Ω

⎛

⎝

⎜

⎞

⎠

⎟= 26dB

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