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CY7C4801/4811/4821
CY7C4831/4841/4851
Document #: 38-06005 Rev. **
Page 7 of 23
Switching Waveforms
Notes:
10. tSKEW1 is the minimum time between a rising (RCLKA,RCLKB) edge and a rising (WCLKA,WCLKB) edge to guarantee that (FFA,FFB) will go HIGH during the current clock
cycle. If the time between the rising edge of (RCLKA,RCLKB) and the rising edge of (WCLKA,WCLKB) is less than tSKEW1, then (FFA,FFB) may not change state until the
next (WCLKA,WCLKB) rising edge.
11. tSKEW1 is the minimum time between a rising (WCLKA,WCLKB) edge and a rising (RCLKA,RCLKB) edge to guarantee that (EFA,EFB) will go HIGH during the current clock
cycle. It the time between the rising edge of (WCLKA,WCLKB) and the rising edge of RCLK is less than tSKEW1, then (EFA,EFB) may not change state until the next
(RCLKA,RCLKB) rising edge.
Write Cycle Timing
tCLKH
tCLKL
NO OPERATION
tDS
tSKEW1
tENS
WENA1
tCLK
tDH
tWFF
tWFF
tENH
WCLKA (WCLKB)
DA0 −DA8
FFA (FFB)
RENA1,RENB2
RCLKA (RCLKB)
48X1–6
NO OPERATION
WENA2(WENB2)
(if applicable)
(WENB1)
(RENB1, RENB2)
(DB0−DB8)
[10]
Read Cycle Timing
tCLKH
tCLKL
NO OPERATION
tSKEW1
tCLK
tOHZ
tREF
tREF
tOE
tENS
tOLZ
tA
tENH
VALID DATA
48X1–7
EFA(EFB)
WCLKA,WCLKB
OEA(OEB)
WENA2(WENB2)
QA0−QA8
(QB0−QB8)
[11]
(RENB1,RENB2)
RENA1,RENA2
WENA1(WENB1)
RCLKA (RCLKB)
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