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CY7C4801/4811/4821
CY7C4831/4841/4851
Document #: 38-06005 Rev. **
Page 2 of 23
Logic Block Diagram
48X1–1
THREE–STATE
OUTPUT REGISTER
READ
CONTROL B
FLAG
LOGIC
WRITE
CONTROL
WRITE
POINTER B
READ
POINTER B
RESET
LOGIC
FLAG
PROGRAM
REGISTER
DB0-8
RCLKB
EFA
PAEA
PAFA
QB0-8
RSA
OEB
RAM
ARRAY A
256x9
.
.
8k x 9
RENB1
RENB2
FFA
WRITE
CONTROL
WRITE
POINTER A
WENA1
WCLKA
WENA2/LDA
RSB
WENB1
WCLKB
WENB2/LDB
RAM
ARRAY B
.
.
8k x 9
READ
CONTROL A
READ
POINTER A
RCLKA
RENA1
RENA2
INPUT
REGISTER
DA
0-8
QA0-8
LDA
LDB
EFB
PAEB
PAFB
FFB
OEA
INPUT
REGISTER
THREE–STATE
OUTPUT REGISTER
256 x9
TQFP
Top View
48X1–1
QA2
QA3
QA4
QA5
QA6
QA7
QA8
Vcc
WENA2/LDA
WCLKA
WENA1
RSA
DA8
DA7
DA6
QA1
QB0
FFB
EFB
OEB
RENB2
RCLKB
RENB1
GND
Vcc
PAEB
PAFB
DB0
DB1
DB2
DB3
DB4
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CY7C4801
CY7C4811
CY7C4821
CY7C4831
CY7C4841
CY7C4851
Pin Configuration
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