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MCT8317A Datasheet(PDF) 117 Page - Texas Instruments |
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MCT8317A Datasheet(HTML) 117 Page - Texas Instruments |
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117 / 161 page  8.7.3.1 PIN_CONFIG1 Register (Offset = A6h) [Reset = 00000000h] PIN_CONFIG1 is shown in Figure 8-68 and described in Table 8-34. Return to the Table 8-32. Register to configure hardware pins Figure 8-68. PIN_CONFIG1 Register 31 30 29 28 27 26 25 24 PARITY DACOUT1_VAR_ADDR R/W-0h R/W-0h 23 22 21 20 19 18 17 16 DACOUT1_VAR_ADDR DACOUT2_VAR_ADDR R/W-0h R/W-0h 15 14 13 12 11 10 9 8 DACOUT2_VAR_ADDR R/W-0h 7 6 5 4 3 2 1 0 DACOUT2_VA R_ADDR BRAKE_INPUT DIR_INPUT SPD_CTRL_MODE Alarm_Pin R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h Table 8-34. PIN_CONFIG1 Register Field Descriptions Bit Field Type Reset Description 31 PARITY R/W 0h Parity bit 30-19 DACOUT1_VAR_ADDR R/W 0h 12-bit address of variable to be monitored on Pin 33 18-7 DACOUT2_VAR_ADDR R/W 0h 12-bit address of variable to be monitored on Pin 34 6-5 BRAKE_INPUT R/W 0h Brake input configuration on Pin 31 0h = Hardware Pin BRAKE 1h = Overwrite Hardware pin with Active Brake 2h = Overwrite Hardware pin with brake functionality disabled 3h = N/A 4-3 DIR_INPUT R/W 0h Direction input configuration on Pin 28 0h = Hardware Pin DIR 1h = Overwrite Hardware pin with clockwise rotation OUTA-OUTB- OUTC 3h = N/A 2-1 SPD_CTRL_MODE R/W 0h Speed input configuration on Pin 24 0h = Analog mode speed Input 1h = PWM Mode Speed Input 2h = I2C Speed Input mode 3h = Frequency based speed Input mode 0 Alarm_Pin R/W 0h Alarm Pin GPIO configuration on Pin 35 0h = Disabled (Hi-Z) 1h = Enabled www.ti.com MCT8317A SLLSFQ2 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 117 Product Folder Links: MCT8317A |
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