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MCT8317A Datasheet(PDF) 121 Page - Texas Instruments |
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MCT8317A Datasheet(HTML) 121 Page - Texas Instruments |
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121 / 161 page ![]() Table 8-36. DEVICE_CONFIG Register Field Descriptions (continued) Bit Field Type Reset Description 3-0 DIG_DEAD_TIME R/W 0h Dead time added by digital controller to gate input signals 0h = 0ns 1h = 50ns 2h = 100ns 3h = 150ns 4h = 200ns 5h = 250ns 6h = 300ns 7h = 350ns 8h = 400ns 9h = 450ns Ah = 500ns Bh = 600ns Ch = 700ns Dh = 800ns Eh = 900ns Fh = 1000ns 8.7.4 Gate_Driver_Configuration Registers Table 8-37 lists the memory-mapped registers for the Gate_Driver_Configuration registers. All register offset addresses not listed in Table 8-37 should be considered as reserved locations and the register contents should not be modified. Table 8-37. GATE_DRIVER_CONFIGURATION Registers Offset Acronym Register Name Section ACh GD_CONFIG1 Gate driver configuration 1 Section 8.7.4.1 AEh GD_CONFIG2 Gate driver configuration 2 Section 8.7.4.2 Complex bit access types are encoded to fit into small table cells. Table 8-38 shows the codes that are used for access types in this section. Table 8-38. Gate_Driver_Configuration Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value www.ti.com MCT8317A SLLSFQ2 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 121 Product Folder Links: MCT8317A |
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