switch node can cause an increase in the current limit

threshold. To avoid this problem, a low Vf Schottky catch

diode must be used (See Catch Diode Selection). Addition-

ally, a resistor can be placed between the ISENSE pin and

the switch node. Any value in the range of 220

Ω to 600Ω is

recommended.

START UP

The current limit circuit is active during start-up. During

start-up the PFET will stay on until either the current limit or

the feedback comparator is tripped

If the current limit comparator is tripped first then the fold

back characteristic should be taken into account. Start-up

into full load may require a higher current limit set point or the

load must be applied after start-up.

One problem with selecting a higher current limit is inrush

current during start-up. Increasing the capacitance (C

parallel with R

and R

activate at a lower current. The output voltage will ramp

more slowly when using this technique. There is example

start-up plot for C

mance Characteristics. Lower values for C

to no effect on soft-start.

EXTERNAL SENSE RESISTOR

The V

perature. This will result an equivalent variation in current

limit. To improve current limit accuracy an external sense

resistor can be connected from V

PFET, as shown in Figure 5. The current sense resistor, R

CS

should have value comparable with R

used, typically in the range of 50m

Ω to 200 mΩ. The equa-

tion in the Current Limit Operation section can be used by

replacing the R

PGATE

When switching, the PGATE pin swings from VIN (off) to

some voltage below VIN (on). How far the PGATE will swing

depends on several factors including the capacitance, on

time, and input voltage.

PGATE voltage swing will increase with decreasing gate

capacitance. Although PGATE voltage will typically be

around VIN-5V, with very small gate capacitances, this value

can increase to a typical maximum of VIN-8.3V.

Additionally, PGATE swing voltage will increase as on time

increases. During long on times, such as when operating at

100% duty cycle, the PGATE voltage will eventually fall to its

maximum voltage of VIN-8.3V (typical) regardless of the

PFET gate capacitance.

The PGATE voltage will not fall below 0.4V (typical). There-

fore, when the input voltage falls below approximately 9V,

the PGATE swing voltage range will be reduced. At an input

voltage of 7V, for instance, PGATE will swing from 7V to a

minimum of 0.4V.

DEVICE ENABLE, SHUTDOWN

The LM3489 can be remotely shutdown by forcing the en-

able pin to ground. With EN pin grounded, the internal blocks

other than the enable logic are de-activated and the shut-

down current of the device will be lowered to only 7µA

(typical). Releasing the EN pin allows for normal operation to

resume. The EN pin is internally pulled high with the voltage

clamped at 8V typical. For normal operation this pin should

be left open. In case an external voltage source is applied to

this pin for enable control, the applied voltage should not

exceed the maximum operating voltage level specified in this

datasheet, i.e. 5.5V.

ADJUSTABLE UVLO

The under-voltage-lockout function can be implemented as

shown in Figure 6. By incorporating the feature of the inter-

nal enable threshold, the lockout level can be programmed

through an external potential divider formed with R3 and R4.

The input voltage information is detected and compared with

the enable threshold and the device operation will be inhib-

ited when V

and hysteresis voltage can be calculated as follows:

20186926

FIGURE 4. Current Limit Fold Back Phenomenon

20186927

FIGURE 5. Current Sensing by External Resistor

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