INPUT CAPACITOR SELECTION (C

A bypass capacitor is required between the input source and

ground. It must be located near the source pin of the external

PFET. The input capacitor prevents large voltage transients

at the input and provides the instantaneous current when the

PFET turns on.

The important parameters for the input capacitor are the

voltage rating and the RMS current rating. Follow the manu-

facturer’s recommended voltage derating. For high input

voltage applications, low ESR electrolytic, Nichicon "UD"

series or the Panasonic "FK" series are available. The RMS

current in the input capacitor can be calculated as follows:

The input capacitor power dissipation can be calculated as

follows.

P

CIN

The input capacitor must be able to handle the RMS current

and the dissipation. Several input capacitors may be con-

nected in parallel to handle large RMS currents. In some

cases it may be much cheaper to use multiple electrolytic

capacitors than a single low ESR, high performance capaci-

tor such as OS-CON or Tantalum. The capacitance value

should be selected such that the ripple voltage created by

the switch current pulses is less than 10% of the total DC

voltage across the capacitor.

swing of the internal gate drive introduces unwanted distur-

bance to the VIN rail and the current limit function can be

affected. In order to eliminate this potential problem, a high

quality ceramic capacitor of 0.1 µF is recommended to filter

out the internal disturbance at the VIN pin. This capacitor

should be placed right next to the VIN pin for best perfor-

mance.

PROGRAMMING THE CURRENT LIMIT (R

The current limit is determined by connecting a resistor

(R

where:

R

I

I

Using the minimum value for I

the current limit threshold will be set higher than the peak

inductor current.

The R

at the ADJ pin does not fall below 3.5V. With this in mind,

R

to set the desired current limit, either use a PFET with a

lower R

Figure 5.

The current limit function can be disabled by connecting the

ADJ pin to ground and ISENSE to VIN.

CATCH DIODE SELECTION (D1)

The important parameters for the catch diode are the peak

current, the peak reverse voltage, and the average power

dissipation. The average current through the diode can be

calculated as following.

I

The off state voltage across the catch diode is approximately

equal to the input voltage. The peak reverse voltage rating

must be greater than input voltage. In nearly all cases a

Schottky diode is recommended. In low output voltage ap-

plications a low forward voltage provides improved effi-

ciency. For high temperature applications, diode leakage

current may become significant and require a higher reverse

voltage rating to achieve acceptable performance.

P-CHANNEL MOSFET SELECTION (Q1)

The important parameters for the PFET are the maximum

Drain-Source voltage (V

rent rating, and the input capacitance.

The voltage across the PFET when it is turned off is equal to

the sum of the input voltage and the diode forward voltage.

The V

the input voltage.

PFET drain current, Id, must be rated higher than the peak

inductor current, I

Depending on operating conditions, the PGATE voltage may

fall as low as V

with a V

GS

maximum rating greater than the maximum

PGATE swing voltage.

As input voltage desreases below 9V, PGATE swing voltage

may also decrease. At 5.0V input the PGATE will swing from

V

and completely, a low threshold PFET should be used when

the input voltage is less than 7V.

Total power loss in the FET can be approximated using the

following equation:

PD

where:

t

t

A value of 10ns to 20ns is typical for ton and toff.

A PFET should be selected with a turn on rise time of less

than 100ns. Slower rise times will degrade efficiency, can

cause false current limiting, and in extreme cases may

cause abnormal spiking at the PGATE pin.

The R

value, R

coefficient. At 100˚C, the R

higher than the 25˚C value. This increase in R

considered when determining R

ADJ

in wide temperature

range applications. If the current limit is set based upon 25˚C

ratings, then false current limiting can occur at high tempera-

ture.

Keeping the gate capacitance below 2000pF is recom-

mended to keep switching losses and transition times low.

This will also help keep the PFET drive current low, which

will improve efficiency and lower the power dissipation within

the controller.

As gate capacitance increases, operating frequency should

be reduced and as gate capacitance decreases operating

frequency can be increased.

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