74F109 datasheet(4/10 Pages) PHILIPS

4 / 10 page

Philips Semiconductors

Product specification

74F109

Postive J-K positive edge-triggered flip-flops

October 23, 1990

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)

SYMBOL

PARAMETER

TEST CONDITIONS1

LIMITS

UNIT

SYMBOL

PARAMETER

TEST CONDITIONS1

MIN

TYP2

MAX

UNIT

High level output voltage

VCC = MIN, VIL = MAX,

IO = MAX

±10%V

2.5

VOH

High-level output voltage

VCC

MIN, VIL

MAX,

VIH = MIN

IOH = MAX

±5%V

2.7

3.4

Low level output voltage

VCC = MIN, VIL = MAX,

IOL = MAX

±10%V

0.30

0.50

VOL

Low-level output voltage

VCC

MIN, VIL

MAX,

VIH = MIN

±5%V

0.30

0.50

VIK

Input clamp voltage

VCC = MIN, II = IIK

–0.73

–1.2

Input current at maximum input voltage

VCC = MAX, VI = 7.0V

100

µA

IIH

High-level input current

VCC = MAX, VI = 2.7V

µA

Low level input current

J, K, CPn

VCC = MAX, VI = 0.5V

–0.6

IIL

Low-level input current

SDn, RDn

VCC = MAX, VI = 0.5V

–1.8

IOS

Short-circuit output current3

VCC = MAX

-60

–150

ICC

Supply current4 (total)

VCC = MAX

12.3

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.

2. All typical values are at VCC = 5V, Tamb = 25°C.

3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold

techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting

of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any

sequence of parameter tests, IOS tests should be performed last.

4. Measure ICC with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.

AC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL

PARAMETER

TEST

CONDITION

VCC = +5.0V

Tamb = +25°C

CL = 50pF

RL = 500Ω

VCC = +5.0V ± 10%

Tamb = 0°C to +70°C

CL = 50pF

RL = 500Ω

VCC = +5.0V ± 10%

Tamb = –40°C to +85°C

CL = 50pF

RL = 500Ω

UNIT

MIN

TYP

MAX

MIN

MAX

MIN

MAX

fMAX

Maximum clock frequency

Waveform 1

125

MHz

tPLH

tPHL

Propagation delay

CPn to Qn or Qn

Waveform 1

3.8

4.4

5.3

6.2

7.0

8.0

3.8

4.4

8.0

9.2

3.8

4.4

9.0

9.2

tPLH

tPHL

Propagation delay

SDn, RD to Qn or Qn

Waveform 2, 3

3.2

3.5

5.2

7.0

9.0

3.2

3.5

8.0

10.5

2.8

3.5

9.0

10.5

AC SETUP REQUIREMENTS

LIMITS

SYMBOL

PARAMETER

TEST

CONDITION

VCC = +5.0V

Tamb = +25°C

CL = 50pF

RL = 500Ω

VCC = +5.0V ± 10%

Tamb = 0°C to +70°C

CL = 50pF

RL = 500Ω

VCC = +5.0V ± 10%

Tamb = –40°C to +85°C

CL = 50pF

RL = 500Ω

UNIT

MIN

TYP

MAX

MIN

MAX

MIN

MAX

tsu (H)

tsu(L)

Setup time, high or low

Dn to CPn

Waveform 1

3.0

th (H)

th (L)

Hold time, high or low

Dn to CPn

Waveform 1

1.0

tw (H)

tw (L)

CP pulse width,

high or low

Waveform 1

4.0

5.0

4.0

5.0

4.0

5.0

tw (L)

SDn or RDn pulse width,

low

Waveform 2

4.0

trec

Recovery time

SDn or RDn to CP

Waveform 3

2.0

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