Philips Semiconductors

Product specification

74F132

Quad 2-input NAND Schmitt trigger

2

1991 Jun 26

853–0342 03094

DESCRIPTION

The 74F132 contains four 2-input NAND gates which accept

standard TTL input signals and provide standard TTL output levels.

They are capable of transforming slowly changing input signals into

sharply defined, jitter-free output signals. In addition, they have

greater noise margin than conventional NAND gates. Each circuit

contains a 2-input Schmitt trigger followed by a Darlington level

shifter and a phase splitter driving a TTL totem-pole output. The

Scmitt trigger uses positive feedback to effectively speed-up slow

input transitions and provide different input threshold voltages for

positive and negative-going transitions. This hysteresis between the

positive-going and negative-going input threshold (typically 800mV)

is determined by resistor ratios and is essentially insensitive to

temperature and supply voltage variations. As long as three inputs

respond in the transition of the other input as shown in Waveform 1.

PIN CONFIGURATION

14

13

12

11

10

7

6

5

4

3

2

1

Q1

D2b

D2a

Q2

Q3

D3b

D3a

D0a

D1b

D0b

Q0

D1a

9

GND

SF00710

8

TYPE

TYPICAL

PROPAGATION

DELAY

TYPICAL

SUPPLY CURRENT

(TOTAL)

74F132

6.3ns

13mA

ORDERING INFORMATION

DESCRIPTION

COMMERCIAL RANGE

PKG DWG #

14-pin plastic DIP

N74F132N

SOT27-1

14-pin plastic SO

N74F132D

SOT108-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F (U.L.) HIGH/LOW

LOAD VALUE HIGH/LOW

Dna, Dnb

Data inputs

1.0/1.0

20

µA/0.6mA

Qn

Data output

50/33

1.0mA/20mA

NOTE: One (1.0) FAST unit load is defined as: 20

µA in the High state and 0.6mA in the Low state.

LOGIC SYMBOL

D0a

D0b

D1a

D2a

D2b

D3a

D3b

D1b

Q0

Q1

Q2

Q3

36

8

11

12

4

5

9

10

12

13

GND = Pin 7

SF00711

IEC/IEEE SYMBOL

1

2

4

5

9

10

12

13

&

3

6

8

11

SF00712