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PCKEP14D Datasheet(PDF) 2 Page - NXP Semiconductors |
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PCKEP14D Datasheet(HTML) 2 Page - NXP Semiconductors |
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2 / 15 page ![]() Philips Semiconductors PCKEP14 2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver Product data Rev. 01 — 30 October 2002 2 of 15 9397 750 09565 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 3. Pinning information 3.1 Pinning 3.2 Pin description 3.2.1 Power supply connection Fig 1. SO20 pin configuration. Fig 2. TSSOP20 pin configuration. 002aaa354 1 2 3 4 5 6 7 8 9 10 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 20 19 18 17 16 15 14 13 12 11 VCC EN VCC CLK1 CLK1 VBB CLK0 CLK0 CLK_SEL VEE 002aaa221 1 2 3 4 5 6 7 8 9 10 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 VCC EN VCC CLK1 CLK1 VBB CLK0 CLK0 CLK_SEL VEE 20 19 18 17 16 15 14 13 12 11 Table 1: Pin description Symbol Pin Description Q0-Q4 1, 3, 5, 7, 9 Positive ECL/PECL output Q0-Q4 2, 4, 6, 8, 10 Negative ECL/PECL output VEE 11 Negative supply CLK_SEL 12 ECL/PECL active clock select input. Pin will default LOW when left open. CLK0, CLK1 13, 16 ECL/PECL/HSTL CLK input. Pins will default LOW when left open. CLK0, CLK1 14, 17 ECL/PECL/HSTL CLK input. Pins will default to VCC/2 when left open. VBB 15 Reference voltage output VCC 18, 20 Positive supply EN 19 ECL synchronous enable CAUTION All VCC and VEE pins must be connected to power supply to guarantee proper operation. MSC895 |
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