74F256 datasheet(6/12 Pages) PHILIPS

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Philips Semiconductors

Product specification

74F256

Dual addressable latch

1988 Nov 29

AC ELECTRICAL CHARACTERISTICS

LIMITS

Tamb = +25°C

Tamb = 0°C to +70°C

SYMBOL

PARAMETER

TEST

VCC = +5V

VCC = +5V ± 10%

UNIT

CONDITION

CL = 50pF, RL = 500Ω

MIN

TYP

MAX

MIN

MAX

tPLH

tPHL

Propagation delay

Dn to Qn

Waveform 2

4.0

3.0

7.0

5.0

9.5

7.0

4.0

2.5

10.0

7.5

tPLH

tPHL

Propagation delay

E to Qn

Waveform 1

4.5

3.0

8.0

5.0

10.5

7.0

4.5

3.0

12.0

7.5

tPLH

tPHL

Propagation delay

An to Qn

Waveform 3

5.0

4.5

10.0

8.5

14.0

9.5

5.0

4.0

14.5

10.0

tPHL

Propagation delay

MR to Qn

Waveform 4

5.0

7.0

9.0

4.5

10.0

AC SETUP REQUIREMENTS

LIMITS

Tamb = +25°C

Tamb = 0°C to +70°C

SYMBOL

PARAMETER

TEST

VCC = +5.0V

VCC = +5.0V ± 10%

UNIT

CONDITION

CL = 50pF, RL = 500Ω

CL= 50pF, RL = 500Ω

MIN

TYP

MAX

MIN

MAX

ts(H)

ts(L)

Setup time, High or Low

Dn to E

Waveform 5

3.0

6.5

3.0

7.0

th(H)

th(L)

Hold time, High or Low

Dn to E

Waveform 5

ts(H)

ts(L)

Setup time, High or Low

An to E1

Waveform 6

2.0

th(H)

th(L)

Hold time, High or Low

An to E2

Waveform 6

tw(L)

E Pulse width, Low

Waveform 1

7.5

8.0

tw(L)

MR Pulse width, Low

Waveform 4

3.0

NOTES:

1. The Address to Enable setup time is the time before the High-to-Low Enable transition that the Address must be stable so that the correct

latch is addressed and the other latches are not affected.

2. The Address to Enable hold time is the time before the Low-to-High Enable transition that the Address must be stable so that the correct

latch is addressed and the other latches are not affected.

74F256 Datasheet(PDF) 6 Page - NXP Semiconductors

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