Philips Semiconductors

Product specification

74F256

Dual addressable latch

1988 Nov 29

3

LOGIC SYMBOL

VCC = Pin 16

GND = Pin 8

E

A0

A1

MR

14

1

2

15

SF00806

Q0a Q1a Q2a Q3a

Q0b Q1b Q2b Q3b

45

6

7

9

10

11

12

313

Da

Db

IEC/IEEE SYMBOL

Z5

3

13

15

5, 7D

1

G4

C7

4R

SF00807

Z6

1

2

14

6, 8D

1

0

1

2

3

C8

4R

0

1

2

3

0

G

0

3

1

4

5

6

7

9

10

11

12

FUNCTION TABLE

INPUTS

OUTPUTS

OPERATING MODE

MR

E

D

A0

A1

Q0

Q1

Q2

Q3

OPERATING MODE

L

H

X

X

X

L

L

L

L

Master Reset

L

L

d

L

L

Q=d

L

L

L

Demultiplex (active-High decoder when D=H)

L

L

d

H

L

L

Q=d

L

L

L

L

d

L

H

L

L

Q=d

L

L

L

d

H

H

L

L

L

Q=d

H

H

X

X

X

q0

q1

q2

q3

Store (do nothing)

H

L

d

L

L

Q=d

q1

q2

q3

H

L

d

H

L

q0

Q=d

q2

q3

Addressable Latch

H

L

d

L

H

q0

q1

Q=d

q3

Addressable Latch

H

L

d

H

H

q0

q1

q2

Q=d

H = High voltage level

L

= Low voltage level

X = Don’t care

d

= High or Low data one setup time prior to the Low-to-High Enable transition

q

= Lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared.