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AD6472 Datasheet(PDF) 2 Page - Analog Devices

Part # AD6472
Description  2 Pair/1 Pair ETSI Compatible HDSL Analog Front End
PDF  8 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD6472 Datasheet(HTML) 2 Page - Analog Devices

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AD6472–SPECIFICATIONS (T
A = TMIN to TMAX unless otherwise noted)
Parameter
Min
Typ
Max
Units
Condition
TRANSMIT CHANNEL
SNR
68
71
dB
The complete transmit path spectrum and pulse
THD
66
71
dB
shape comply with ETSI requirements.
TRANSMIT DAC
The transmit DAC maximum update rate is half
Clock Frequency
18.688
MHz
the maximum output data rate, i.e., 1168 kHz.
Resolution
12
Bits
The maximum transmit clock is 16
× 1168 =
Update Rate
1168
kHz
18.688 MHz.
Output Voltage
2
V p-p Diff
TRANSMIT FILTER
Corner Frequency (3 dB)
1
320
kHz
MODE_SEL1 = 0
535
kHz
MODE_SEL1 = 1
Accuracy
±5
±10
%
Gain
9.53
dB
3.53
dB
LINE DRIVER
VCM
2.5
V
Transformer Turns Ratio = 1:2.3 at 50 kHz
Output Power
13.5
dBm
When Loaded by ETSI (RTR/TM3036)
Output Voltage
6
V p-p Diff
HDSL Test Loops
TRANSMIT VOLTAGE LEVEL
6
V p-p Diff
TX_GAIN = 0
3
V p-p Diff
TX_GAIN = 1
RECEIVE CHANNEL
SNR
68
71
dB
THD
66
71
dB
HYBRID INTERFACE
VCM = 2.5 V. See Figure 3
Input Voltage Range
5
V p-p Diff
Input Impedance
10
k
PROGRAMMABLE GAIN AMPLIFIER
Condition –6 dB to +9 dB
Overall Gain Accuracy
±1dB
Gain Step
3
dB
Gain Step Accuracy
±0.25
dB
RECEIVE FILTER
Corner Frequency (–3 dB)
1
320
kHz
MODE_SEL1 = 0
640
kHz
MODE_SEL1 = 1
Accuracy
±5
±10
%
TIMING RECOVERY DAC
Resolution
7
Bits
Guaranteed Monotonic
Output Low
0.5
V
Output High
4.5
V
DIGITAL INTERFACE
5 V Supply, VMIN to VMAX
Input Logic High, VIH
3.3
V
Input Logic LOW, VIL
0.8
V
Output Logic High, VOH
VDD – 0.3
V
Output Logic Low, VOL
0.4
V
3.3 V Supply, VMIN to VMAX
Input Logic High, VIH
2.0
V
Input Logic Low, VIL
0.2
V
Output Logic High, VOH
VDD – 0.3
V
POWER SUPPLY VOLTAGE
VMIN to VMAX
4.75
5
5.25
V
5 V Supply
3.15
3.3
3.45
V
3.3 V Supply
POWER SUPPLY CURRENT
VMIN to VMAX, TMIN to TMAX
Normal Mode, Excl. Driver
65
mA
5 V Supply, MODE_SEL1 = 0
OVRSAMP Mode
73
mA
5 V Supply, MODE_SEL1 = 1, MODE_SEL0 = 1
Line Driver
50
mA
With 50
Ω Differential Load
Low Power Mode
17
mA
OPERATING TEMPERATURE RANGE
–40
+85
°CT
MIN to TMAX
NOTES
1The ADC clock period t(1
÷ f) is used for the dynamic tuning of the Tx and Rx filters.
Specifications subject to change without notice.



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