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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

WED2ZLRSP01S

April, 2002

Rev. 0

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

AC CHARACTERISTICS

NOTES:

1. All Address inputs must meet the specified setup and hold times for all rising clock (CK) edges when ADV is sampled low and CEx# is

sampled valid. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.

2. Chip enable must be valid at each rising edge of CK (when ADV is Low) to remain enabled.

3. A write cycle is defined by WE# low having been registered into the device at ADV Low. A Read cycle is defined by WE# High with ADV Low.

Both cases must meet setup and hold times.

4. Applies to each of the independent arrays.

OUTPUT LOAD (A)

OUTPUT LOAD (B)

Parameter

Symbol

166MHz

150MHz

133MHz

100MHz

Units

Min

Max

Min

Max

Min

Max

Min

Max

Clock Time

6.0

6.7

7.5

10.0

ns

Clock Access Time

—

3.5

—

3.8

—

4.2

—

5.0

ns

Output enable to Data Valid

—

3.5

—

3.8

—

4.2

—

5.0

ns

Clock High to Output Low-Z

1.5

—

1.5

—

1.5

—

1.5

—

ns

Output Hold from Clock High

1.5

—

1.5

—

1.5

—

1.5

—

ns

Output Enable Low to output Low-Z

0.0

—

0.0

—

0.0

—

0.0

—

ns

Output Enable High to Output High-Z

—

3.0

—

3.0

—

3.5

—

3.5

ns

Clock High to Output High-Z

—

3.0

—

3.0

—

3.5

—

3.5

ns

Clock High Pulse Width

2.2

—

2.5

—

3.0

—

3.0

—

ns

Clock Low Pulse Width

2.2

—

2.5

—

3.0

—

3.0

—

ns

Address Setup to Clock High

1.5

—

1.5

—

1.5

—

1.5

—

ns

CKE# Setup to Clock High

1.5

—

1.5

—

1.5

—

1.5

—

ns

Data Setup to Clock High

1.5

—

1.5

—

1.5

—

1.5

—

ns

Write Setup to Clock High

1.5

—

1.5

—

1.5

—

1.5

—

ns

Address Advance to Clock High

1.5

1.5

1.5

1.5

ns

Chip Select Setup to Clock High

1.5

1.5

1.5

1.5

ns

Address Hold to Clock high

0.5

—

0.5

—

0.5

—

0.5

—

ns

CKE# Hold to Clock High

0.5

—

0.5

—

0.5

—

0.5

—

ns

Data Hold to Clock High

0.5

—

0.5

—

0.5

—

0.5

—

ns

Write Hold to Clock High

0.5

—

0.5

—

0.5

—

0.5

—

ns

Address Advance to Clock High

0.5

—

0.5

—

0.5

—

0.5

—

ns

Chip Select Hold to Clock High

0.5

—

0.5

—

0.5

—

0.5

—

ns

*Including Scope and Jig Capacitance

AC TEST CONDITIONS

Parameter

Value

Input Pulse Level

0 to 2.5V

Input Rise and Fall Time (Measured at 20% to 80%)

1.0V/ns

Input and Output Timing Reference Levels

1.25V

Output Load

See Output Load (A)

Dout

Zo=50

Ω

RL=50

Ω

VL=1.25V

30pF*

Dout

1538

Ω

5pF*

+2.5V

1667

Ω