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Military Plastic pASIC 3 Family
QL3060 Clock Cells
I/O Cells
Notes:
[7] The array distributed networks consist of 88 half columns and the global distributed networks
consist of 92 half columns, each driven by an independent buffer. The number of half columns
used does not affect clock buffer delay. The array clock has up to 18 loads per half column. The
global clock has up to 20 loads per half column.
[8] The following loads are used for tPXZ:
Symbol
Parameter
Propagation Delays (ns)
Loads per Half Column [7]
1
2348
10
12
14
16
18
20
tACK
Array Clock Delay
1.2
1.2
1.3
1.3
1.5
1.6
1.7
1.8
1.9
2
2.1
tGCKP
Global Clock Pin Delay
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
tGCKB
Global Clock Buffer Delay
0.8
0.8
0.9
0.9
1.1
1.2
1.3
1.4
1.5
1.6
1.7
Symbol
Parameter
Propagation Delays (ns)
Fanout [5]
12
3
4
8
10
tI/O
Input Delay (bidirectional pad)
1.3
1.6
1.8
2.1
3.1
3.6
tISU
Input Register Set-Up Time
3.1
3.1
3.1
3.1
3.1
3.1
tIH
Input Register Hold Time
0.0
0.0
0.0
0.0
0.0
0.0
tlOCLK
Input Register Clock To Q
0.7
1.0
1.2
1.5
2.5
3.0
tlORST
Input Register Reset Delay
0.6
0.9
1.1
1.4
2.4
2.9
tlESU
Input Register clock Enable Set-Up Time
2.3
2.3
2.3
2.3
2.3
2.3
tlEH
Input Register Clock Enable Hold Time
0.0
0.0
0.0
0.0
0.0
0.0
Symbol
Parameter
Propagation Delays (ns)
Output Load Capacitance (pF)
30
50
75
100
150
tOUTLH
Output Delay Low to High
2.1
2.5
3.1
3.6
4.7
tOUTHL
Output Delay High to Low
2.2
2.6
3.2
3.7
4.8
tPZH
Output Delay Tri-state to High
1.2
1.7
2.2
2.8
3.9
tPZL
Output Delay Tri-state to Low
1.6
2.0
2.6
3.1
4.2
tPHZ
Output Delay High to Tri-State [8]
2.0
tPLZ
Output Delay Low to Tri-State [8]
1.2
5 pF
1K
Ω
5 pF
1K
Ω
tPHZ
tPLZ
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