V3023 datasheet(13/15 Pages) EMMICRO

13 / 15 page

V3023

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How to Determine the Digital Trimming Value

The value to write into the digital trimming register has to

be determined by the following procedure:

1. Initialise the V3023 by writing a 1 and then a 0 into the

"Initialisation Bit" of the status register 2 (addr. 02 hex,

bit 4). This activates the frequency tuning mode in

status register 0 (addr. 00 hex, bit 1) and clears the

other status bits.

2. Write the value 00 hex into the digital trimming register

(addr 10 hex).

From now, the IRQ output (open

drain) will deliver the 100 Hz signal, which has a 20%

duty cycle.

3. Measure the duration of 21 pulses at the IRQ output,

with the trigger set for the falling edge. It is possible

also to divide the IRQ frequency by 21, using a TTL

or CMOS external circuit.

4. Compute the frequency error in ppm:

freq. error =

210ms

value

measured

210ms

−

x 10

5. Compute the corrective value to write into the digital

trimming register.

Digital trimming value = frequency error / 0.984

6. Write this value into the digital trimming register.

7. Switch off the frequency tuning mode in status 0 (addr.

00 hex, bit 0 set to 0).

The Real Time Clock circuit will now run accurately at an

operating

temperature

equal

the

calibration

temperature. If the operating temperature differs from the

one at calibration time, the graphs shown on Fig. 4 and 5

will help in determining the definitive value. If the mean

operating temperature of the equipment is not known at

calibration time, the equipment user will do the final

correction with a software provided by the system

designer. To avoid the calibration procedure, it is possible

also to set the digital trimming register to 210 (D2 hex) as

a standard starting value, and let the final equipment user

perform the final adjustment on site, which will take the

real temperature into account.

Time Correction at Room Temperature

Let us consider that the duration of 21 pulses of the IRQ

signal is 209.97 ms at room temperature.

The frequency error is:

(210 – 209.97) / 210 x 1E + 06 = 142.857 ppm

The value for the digital trimming register is:

142.857 / 0.984 = 145.18, rounded up to 145 ppm (91

hex)

Time Correction with Change of Temperature

If the mean temperature on site is known to be 45°C, the

frequency error determined at room temperature has to be

modified using the graphs or the equation of Fig. 5

∆f/f = -0.038 x (45-25)

2 = 15.2 ppm

The trimming value for 45°C will be:

(142.857 ppm – 15.2 ppm) / 0.984 = 129.73, rounded to

130 (82 hex)

12 / 24 Hour Data Format

The V3023 can run in 12 hour data format.

initialisation the 12/24 hour bit addr. 00 bit 4 is cleared

putting the V3023 in 24 hour data format. If the 12 hour

data format is required then bit 4 at addr. 00 must be set.

In the 12 hour data format the AM/PM indicator is the

MSB of the hours register addr. 23 bit 7.

A set bit

indicates PM. When reading the hours in the 12 hour

data format software should mask the MSB of the hours

zero.

The internal clock registers change automatically between

12 and 24 hour mode when the 24/12 hour bit is changed.

The alarm hours however must be rewritten.

Test

From the various test features added to the V3023 some

may be activated by the user. Table 6 shows the test bits.

Table 10 shows the three available modes and how they

may be activated.

The first accelerates the incrementing of the parameters

in the reserved clock and timer area by 32.

The second causes all clock and timer parameters, in the

reserved clock and timer area, to be incremented in

parallel at 100 Hz with no carry over, ie. independently of

each other.

The third test mode combines the previous two resulting

in parallel incrementing at 3.2 kHz.

While test bit 1 is set (addr. 00 hex, bit 7) the digital

trimming action is disabled and no pulses are removed

from the divider chain. Test bit 0 (addr. 00 hex, bit 6) can

be combined with digital trimming (see section "Frequency

Tuning").

To leave test, the test bits (addr 00 hex, bits 6 and 7) must

be cleared by software. Test corrupts the clock and timer

parameters and so all parameters should be re-initialised

after a test session.

Test Modes

Addr.

00hex bit 7

Addr.

00hex bit 6

Function

Normal operation

Acceleration by 32

Parallel increment of all clock

and timer parameters at 100

with

carry

over;

dependent on the status of bit

3 at address 00 hex

Parallel increment of all clock

and timer parameters at 3.2

kHz

with

carry

over;

dependent on the status of bit

3 at address 00 hex

Table 10

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