R

V6116

Copyright

© 2005, EM Microelectronic-Marin SA

2

www.emmicroelectronic.com

Absolute Maximum Ratings

Parameter

Symbol

Conditions

Supply voltage range

-0.3V to 9V

LCD supply voltage range

-0.3V to 9.5V

Voltage at DI, DO, CLK, STR,

FR, COL

-0.3V to

Voltage at V1 to V3, S1 to S40

0.3V

Storage temperature range

-65 to +150°C

Electrostatic discharge max. to

MIL-STD-883C method 3015.7

1000V

Maximum soldering conditions

290°C x 10s

Table 1

Stresses above these listed maximum ratings may cause

permanent damages to the device. Exposure beyond

specified operating conditions may affect device reliability

or cause malfunction.

Handling Procedures

This device has built-in protection against high static

voltages or electric fields; however, anti-static precautions

must be taken as for any other CMOS component. Unless

otherwise specified, proper operation can only occur when

all terminal voltages are kept within the voltage range.

Unused inputs must always be tied to a defined logic

voltage level.

Operating Conditions

Parameter

Symbol Min

Typ

Max Unit

Operating

Temperature

-40

+85

°C

Logic supply voltage

2

5

6

V

LCD supply voltage

2

5

9

V

Table 2

Electrical Characteristics

Parameter

Symbol

Test Conditions

Min.

Typ.

Max.

Units

Dynamic supply current

See note 1

150

250

µA

Dynamic supply current

0.1

1

µA

Dynamic supply current

See note 1

3

12

µA

Dynamic supply current

See note 2

200

250

µA

Standby supply current

0.1

1

µA

Control Signals DI, CLK, STR, FR

and COL

Input leakage

1

1000

nA

Input capacitance

8

pF

Low level input voltage

0

0.8

V

High level input voltage for DI, STR,

FR and COL

2.0

V

High level input voltage for CLK

3.0

V

Data Output DO

High level output voltage

2.4

V

Low level output voltage

0.4

V

Driver Outputs S1 … S40

Driver impedance (note 4)

1.0

1.5

k

Ω

Driver impedance (note 4)

2.6

3.5

k

Ω

Driver impedance (note 4)

7

k

Ω

Bias impedance V1, V2, V3 (note 5)

18

24

k

Ω

Bias impedance V1, V2, V3 (note 5)

20

27

k

Ω

Bias impedance V1, V2, V3 (note 5)

24

k

Ω

DC output component

± VDC

see Tables 4a & 4b,

30

50

mV

Table 3

Note 1

Note 2

Note 3

Note 4

: This is the impedance between of the voltage bias level pins (V1, V2 or V3) and the output pins S1 to S40 when a

given voltage bias level is driving the outputs (S1 to S40)

Note 5

: This is the impedance seen at the segment pin. Outputs measured one at a time.