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74HC165 Datasheet(PDF) 9 Page - NXP Semiconductors |
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74HC165 Datasheet(HTML) 9 Page - NXP Semiconductors |
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9 / 10 page  December 1990 9 Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74HC/HCT165 AC WAVEFORMS Fig.6 Waveforms showing the clock (CP) to output (Q7 or Q7) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. The changing to output assumes internal Q6 opposite state from Q7. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the parallel load (PL) pulse width, the parallel load to output (Q7 or Q7) propagation delays, the parallel load to clock (CP) and clock enable (CE) removal time. The changing to output assumes internal Q6 opposite state from Q7. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the data input (Dn) to output (Q7 or Q7) propagation delays when PL is LOW. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. |
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