Data Sheet

ADRF5049

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 7 of 14

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

EN

Enable Input. See Table 6 for the truth table and Figure 7 for the control interface schematic.

2

V1

Control Input 1. See Table 6 for the truth table and Figure 6 for the control interface schematic.

3, 5, 9, 11 to 13, 15 to 17, 19

to 21, 23

GND

Ground.

4

RFC

RF Common Port. The RFC pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is required when the

RF line potential is equal to 0 V dc. See Table 6 for the truth table and Figure 5 for the interface schematic.

6

VSS

Negative Supply Voltage.

7

LS

Logic Select. See Table 6 for the truth table and Figure 7 for the control interface schematic.

8

VDD

Positive Supply Voltage.

10

RF4

RF Throw Port 4. The RF4 pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is required when the

RF line potential is equal to 0 V dc. See Table 6 for the truth table and Figure 5 for the interface schematic.

14

RF3

RF Throw Port 3. The RF3 pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is required when the

RF line potential is equal to 0 V dc. See Table 6 for the truth table and Figure 5 for the interface schematic.

18

RF2

RF Throw Port 2. The RF2 pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is required when the

RF line potential is equal to 0 V dc. See Table 6 for the truth table and Figure 5 for the interface schematic.

22

RF1

RF Throw Port 1. The RF1 pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is required when the

RF line potential is equal to 0 V dc. See Table 6 for the truth table and Figure 5 for the interface schematic.

24

V2

Control Input 2. See Table 6 for the truth table and Figure 6 for the control interface schematic.

EPAD

Exposed Pad. The exposed pad must be connected to the RF and dc ground of the PCB.