Data Sheet

ADRF5049

THEORY OF OPERATION

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Rev. 0 | 12 of 14

The ADRF5049 requires a positive supply voltage applied to the

VDD pin and a negative supply voltage applied to the VSS pin.

Bypassing capacitors are recommended on the supply lines to

minimize RF coupling.

All of the RF ports (RFC, RF1 to RF4) are dc-coupled to 0 V,

and no dc blocking is required at the RFx ports when the RF line

potential is equal to 0 V. The RF ports are internally matched to 50

Ω. Therefore, external matching networks are not required.

The ADRF5049 integrates a driver to perform logic functions inter-

nally and to provide the user with the advantage of a simplified

CMOS-/LVTTL-compatible control interface. The driver features four

digital control input pins (EN, LS, V1, and V2) that control the state

of the RFx paths. See Table 6.

The LS pin allows the user to define the control input logic se-

quence for the RF path selections. The logic level applied to the V1

and V2 pins determines which RFx port is in the insertion loss state

while the other three paths are in the isolation state.

When the EN pin is logic high, all four RFx paths are in an isolation

state regardless of the logic state of LS, V1, and V2. The RFx

ports are terminated to internal 50 Ω resistors, and RFC becomes

reflective.

The insertion loss path conducts the RF signal between the select-

ed RF throw port and the RF common port. The switch design is

bidirectional with equal power handling capabilities. The RF input

signal can be applied to the RFC port or the selected RF throw

port. The isolation paths provide high loss between the insertion

loss path and the unselected RF throw ports that are terminated to

internal 50 Ω resistors.

The ideal power-up sequence is as follows:

1. Connect GND.

2. Power up VDD.

3. Apply the digital control inputs: EN, LS, V1, and V2. Applying

digital control inputs before the VDD supply can inadvertently

forward bias and damage the internal ESD protection struc-

tures. A series 1 kΩ resistor can be used to limit the current

flowing into the digital control input pins in such cases. If the

digital control input pins are not driven to a valid logic state (that

is, the controller output is in high impedance state) after VDD is

powered up, it is recommended to use pull-up and power-down

resistors.

4. Apply an RF input signal.

The ideal power-down sequence is the reverse order of the power-

up sequence.

Table 6. Control Voltage Truth Table

Digital Control Inputs

RFx Paths

EN

LS

V1

V2

RF1 to RFC

RF2 to RFC

RF3 to RFC

RF4 to RFC

Low

Low

Low

Low

Insertion loss (on)

Isolation (off)

Isolation (off)

Isolation (off)

Low

Low

High

Low

Isolation (off)

Insertion loss (on)

Isolation (off)

Isolation (off)

Low

Low

Low

High

Isolation (off)

Isolation (off)

Insertion loss (on)

Isolation (off)

Low

Low

High

High

Isolation (off)

Isolation (off)

Isolation (off)

Insertion loss (on)

Low

High

Low

Low

Isolation (off)

Isolation (off)

Isolation (off)

Insertion loss (on)

Low

High

High

Low

Isolation (off)

Isolation (off)

Insertion loss (on)

Isolation (off)

Low

High

Low

High

Isolation (off)

Insertion loss (on)

Isolation (off)

Isolation (off)

Low

High

High

High

Insertion loss (on)

Isolation (off)

Isolation (off)

Isolation (off)

High

Low or high Low or high Low or high Isolation (off)

Isolation (off)

Isolation (off)

Isolation (off)