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AM68AX Datasheet(PDF) 158 Page - Texas Instruments

Part # AM68AX
Description  AM68Ax Processors, Silicon Revision 1.0
PDF  251 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
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AM68AX Datasheet(HTML) 158 Page - Texas Instruments

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Table 7-32. DPI Timing Conditions
PARAMETER
MIN
MAX
UNIT
INPUT CONDITIONS
SRI
Input slew rate
1.44
26.4
V/ns
OUTPUT CONDITIONS
CL
Output load capacitance
1.5
5
pF
PCB CONNECTIVITY REQUIREMENTS
td(Trace Mismatch Delay)
Propagation delay mismatch
across all traces
100
ps
Table 7-33, Table 7-34, Figure 7-42 and Figure 7-43 assume testing over the recommended operating conditions
and electrical characteristic conditions.
Table 7-33. DPI Video Output Switching Characteristics
NO.(2)
PARAMETER
MIN
MAX
UNIT
D1
tc(pclk)
Cycle time, VOUT(x)_PCLK
6.06
ns
D2
tw(pclkL)
Pulse duration, VOUT(x)_PCLK low
0.475×P(1)
ns
D3
tw(pclkH)
Pulse duration, VOUT(x)_PCLK high
0.475×P(1)
ns
D4
td(pclkV-dataV)
Delay time, VOUT(x)_PCLK transition to VOUT(x)_DATA[23:0]
transition
-0.68
1.78
ns
D5
td(pclkV-ctrlL)
Delay time, VOUT(x)_PCLK transition to control signals
VOUT(x)_VSYNC, VOUT(x)_HSYNC, VOUT(x)_DE falling edge
-0.68
1.78
ns
(1)
P = output VOUT(x)_PCLK period in ns.
(2)
x in VOUT(x) = 1 or 2
VOUT(x)_PCLK
VOUT(x)_VSYNC
VOUT(x)_HSYNC
VOUT(x)_DATA[23:0]
VOUT(x)_DE
data_1 data_2
data_n
D1
D2
D3
D5
D5
D4
D5
DPI_TIMING_01
VOUT
_PCLK
(x)
Falling-edge Clock Reference
Rising-edge Clock Reference
A.
The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.
B.
The polarity and the pulse width of VOUT(x)_HSYNC and VOUT(x)_VSYNC are programmable, refer to Display Subsystem (DSS)
section in Peripherals chapter in the device TRM.
C.
The VOUT(x)_PCLK frequency can be configured, refer to Display Subsystem section in Peripherals chapter in the device TRM.
D.
x in VOUT(x) = 1 or 2.
Figure 7-42. DPI Video Output
AM68A
SPRSP91 – FEBRUARY 2023
www.ti.com
158
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Product Folder Links: AM68A



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