AM68AX datasheet(157/251 Pages) TI

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7.10.5.3 CSI-2

Note

For more information, see the Camera Streaming Interface Receiver (CSI_RX_IF) chapter in the

device TRM.

The CSI_RX_IF deals with the processing of the pixel data coming from an external image sensor and data from

memory. It is a key component for the following multimedia applications: camera viewfinder, video record, and

still image capture.

The CSI_RX_IF has a primary serial interface (CSI-2 port) compliant with the MIPI D-PHY RX specification v1.2

and the MIPI CSI-2 specification v1.3, with 4 differential data lanes plus 1 differential clock lane in synchronous

mode, double data rate. Refer to the specification for timing details.

• 2.5 Gbps (1.25 GHz) for each lane.

7.10.5.4 DDRSS

For more details about features and additional description information on the device LPDDR4 Memory

Interfaces, see the corresponding sections within Section 6.3 and Detailed Description.

The device has dedicated interface to LPDDR4. It supports JEDEC JESD209-4B standard compliant LPDDR4

SDRAM devices with the following features:

• 32-bit data path to external SDRAM memory

• Memory device capacity: Up to 8GB address space available over two chip selects (4GB per rank)

• No support for byte mode LPDDR4 memories, or memories with more than 17 row address bits

Table 7-31 and Figure 7-41 present switching characteristics for DDRSS.

Table 7-31. Switching Characteristics for DDRSS

NO.

PARAMETER

DDR TYPE

MIN

MAX

UNIT

tc(DDR_CKP/DDR_CKN)

Cycle time, DDR0_CKP and DDR0_CKN

LPDDR4

0.468#uniq

ue_249/

unique_24

9_Connect

_42_T5681

413-1refer

enceTitle

3.003

1. Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system

and by PCB implementation. TI strongly recommends all designs to follow the TI LPDDR4 EVM PCB

layout exactly in every detail (routing, spacing, vias/backdrill, PCB material, etc.) in order to achieve the full

specified clock frequency. Refer to the Jacinto 7 DDR Board Design and Layout Guidelines for details.

DDR0_CKP

DDR0_CKN

Figure 7-41. DDRSS Memory Interface Clock Timing

For more information, see DDR Subsystem (DDRSS) section in Memory Controllers chapter in the device TRM.

7.10.5.5 DSS

For more details about features and additional description information on the device Display Subsystem – Video

Output Ports, see the corresponding sections within Section 6.3 and Detailed Description.

Table 7-32 represents DPI timing conditions.

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AM68A

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