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Spread Aware™, Zero Delay Buffer
W162
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07150 Rev. *A
Revised December 14, 02
Features
• Spread Aware™—designed to work with SSFTG
reference signals
• Two banks of four outputs, plus the fed back output
• Outputs may be three-stated
• Available in 16-pin SOIC or SSOP package
• Extra strength output drive available (-19 version)
• Internal feedback
Key Specifications
Operating Voltage: ............................................... 3.3V±10%
Operating Range: ................................15 < fOUT < 133 MHz
Cycle-to-Cycle Jitter: .................................................. 250 ps
Output to Output Skew: ............................................. 150 ps
Propagation Delay: ..................................................... 150 ps
Table 1. Input Logic
SEL1
SEL0
QA0:3
QB0:3
PLL
QFB
00
Three-
State
Three-
State
Shutdown
Active
01
Active
Three-
State
Active,
Utilized
Active
1
0
Active
Active
Shutdown,
Bypassed
Active
1
1
Active
Active
Active,
Utilized
Active
Spread Aware is a trademark of Cypress Semiconductor Corporation.
Block Diagram
Pin Configuration
PLL
REF
MUX
QA1
QA2
QA3
QB0
QB1
SEL0
QB2
QB3
SEL1
QFB
QA3
QA2
VDD
GND
QB3
QB2
SEL0
16
15
14
13
12
11
10
9
REF
QA0
QA1
VDD
GND
QB0
QB1
SEL1
1
2
3
4
5
6
7
8
QFB
QA0
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