September 1993

2

Philips Semiconductors

Product specification

Octal bus transceiver/register; 3-state

74HC/HCT646

FEATURES

• Independent register for A and B buses

• Multiplexed real-time and stored data

• Output capability: bus driver

GENERAL DESCRIPTION

The 74HC/HCT646 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT646 consist of bus transceiver circuits with

3-state outputs, D-type flip-flops, and control circuitry

arranged for multiplexed transmission of data directly from

the internal registers. Data on the “A” or “B” bus will be

clocked into the registers as the appropriate clock

enable (OE) and direction (DIR) inputs are provided to

control the transceiver function. In the transceiver mode,

data present at the high-impedance port may be stored in

either the “A” or “B” register, or in both. The select source

(transparent mode) data. The direction (DIR) input

determines which bus will receive data when OE is active

(LOW). In the isolation mode (OE = HIGH), “A” data may

be stored in the “B” register and/or “B” data may be stored

in the “A” register.

When an output function is disabled, the input function is

still enabled and may be used to store and transmit data.

Only one of the two buses, A or B, may be driven at a time.

The “646” is functionally identical to the “648”, but has

non-inverting data paths.

QUICK REFERENCE DATA

Notes

ORDERING INFORMATION

See

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HC

HCT

propagation delay

11

13

ns

maximum clock frequency

69

85

MHz

input capacitance

3.5

3.5

pF

power dissipation capacitance per channel

notes 1 and 2

30

33

pF