74HC7597 datasheet(2/12 Pages) PHILIPS

2 / 12 page

December 1990

Philips Semiconductors

Product speciﬁcation

8-bit shift register with input latches

74HC/HCT7597

FEATURES

• 8-bit parallel input latches

• Shift register has direct overriding load and clear

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT7597 are high-speed Si-gate CMOS

devices and are pin compatible with low power Schottky

TTL (LSTTL). They are specified in compliance with

JEDEC standard no. 7A.

The 74HC/HCT7597 both consist of an 8-bit storage latch

feeding a parallel-in, serial-out 8-bit shift register.

When LE is LOW, data at the Dn inputs enter the latches.

In this condition the latches are transparent, i.e. a latch

output will change state each time its corresponding

D-input changes.

When LE is HIGH the latches store the information that

was present at the D-inputs, a set-up time preceding the

LOW-to-HIGH transition of LE.

The shift register has a positive edge-triggered clock,

direct load (from storage) and clear inputs.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C; tr =tf = 6 ns

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz; fo = output frequency in MHz

∑ (CL × VCC2 × fo) = sum of outputs

CL = output load capacitance in pF; VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC − 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HCT

tPHL/ tPLH

propagation delay

CL = 15 pF; VCC = 5 V

SHCP to Q

LE to Q

PL to Q

D7 to Q

fmax

maximum clock frequency SHCP

MHz

input capacitance

3.5

CPD

power dissipation capacitance per package

notes 1, 2

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