ADC34RF52 datasheet(46/105 Pages) TI

46 / 105 page

7.3.6 JESD204B Interface

The ADC34RF52 uses the JESD204B high-speed serial interface to transfer data from the ADC to the receiving

logic device. ADC34RF52 serialized lanes are capable of operating up to 13 Gbps, slightly above the JESD204B

max lane rate. A maximum of 8 lanes can be used to allow lower lane rates for interfacing with speed limited

logic devices. Figure 7-38 shows a simplified block diagram of the JESD204B interface.

ADC

JESD204B

TRANSPORT

LAYER

SCRAMBLER

(Optional)

JESD204B

LINK LAYER

8B/10B

ENCODER

JESD204B

ADC

JESD204B BLOCK

Figure 7-38. JESD204B Block Diagram

7.3.6.1 JESD204B Initial Lane Alignment (ILA)

The receiving device starts the initial lane alignment process by deasserting the SYNC signal. When a logic

low state is detected on the SYNC input, the ADC starts transmitting comma characters (K28.5) to establish

the code group synchronization, as shown in Figure 7-39. When synchronization is completed, the receiving

device reasserts the SYNC signal and the ADC starts the initial lane alignment sequence with the next local

multi-frame clock (LMFC) boundary. The ADC transmits four multi-frames, each containing K frame (K is SPI

programmable). EAch of the multi-frames contains the frame start and frame end symbols. The second multi-

frame also contains the JESD204B link configuration data.

SYNC

SYSREF

LMFC Clock

LMFC Boundary

xxx

Transmit Data

K28.5

ILA

DATA

Multi-

Frame

Code Group Synchronization

Initial Lane Alignment

Data Transmission

Figure 7-39. JESD204B Internal Timing Diagram

7.3.6.1.1 SYNC Signal

The SYNC signal can be issued using one of two different methods:

• One of the GPIO1/2 pins can be configured via SPI to become the SYNC input pin (address 0x234 in the

digital page)

• The synchronization command can be issued via SPI register write (address 0x21 in the JESD page)

When using the GPIO1/2 pins for the SYNC signal input, the device also supports the option to invert the signal

polarity (address 0x236 in the digital page).

ADC34RF52

SBASAI7 – MARCH 2023

www.ti.com

Submit Document Feedback

Product Folder Links: ADC34RF52

ADC34RF52 Datasheet(PDF) 46 Page - Texas Instruments

ADC34RF52 Datasheet(HTML) 46 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL