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ADC34RF52 Datasheet(PDF) 70 Page - Texas Instruments |
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ADC34RF52 Datasheet(HTML) 70 Page - Texas Instruments |
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70 / 105 page  Table 7-67. Register 0x27 Field Descriptions (continued) Bit Field Type Reset Description 0 0 R/W 0 Must write 0 Figure 7-65. Register 0x28 (JESD page) 7 6 5 4 3 2 1 0 JESD LANE EN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-68. Register 0x28 Field Descriptions Bit Field Type Reset Description 7-0 JESD LANE EN R/W 11111111 This register turns on individual output lanes 0: Lane powered down 1: Serdes lane enabled D0: Lane DOUT0 D1: Lane DOUT1 ... D7: Lane DOUT7 Figure 7-66. Register 0x2B (JESD page) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 SYNC INV R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-69. Register 0x2B Field Descriptions Bit Field Type Reset Description 7-1 0 R/W 0 Must write 0 0 SYNC INV R/W 0 This register inverts the polarity from external SYNC pin 0: Polarity as is 1: Polarity inverted Figure 7-67. Register 0x2D (JESD page) 7 6 5 4 3 2 1 0 0 0 0 0 0 JESD SEQ SEL R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-70. Register 0x2D Field Descriptions Bit Field Type Reset Description 7-3 0 R/W 0 Must write 0 2-0 JESD SEQ SEL R/W 000 This register selects the JESD test pattern sequence 0: Test sequence disabled 1: Repeat D21.5 high frequency pattern for random jitter (RJ) 2: Repeat K28.5 mixed frequency pattern for deterministic jitter (DJ) 3: Repeat initial lane alignment (ILA) sequence 4: Modified random pattern 5: Scrambled jitter pattern 6: Repeat K28.7 low frequency pattern 7: Short test pattern ADC34RF52 SBASAI7 – MARCH 2023 www.ti.com 70 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: ADC34RF52 |
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