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EFP01 Datasheet(PDF) 43 Page - Silicon Laboratories |
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EFP01 Datasheet(HTML) 43 Page - Silicon Laboratories |
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43 / 158 page  Table 5.4. I2C Timing Parameter Symbol Test Condition Min Typ Max Unit Hysteresis VHYS High-to-low versus low-to-high transition VIO*0.05 — — V SCL Frequency fSCL EFP01 is one of multiple peripher- als on I2C bus, CLOAD ≤ 25pF — — 400 kHz EFP01 is sole peripheral on I2C bus, CLOAD ≤ 25 pF — — 1000 kHz SCL High Time tSKH fSCL = 400 kHz, CLOAD = 25 pF 0.6 — — µs SCL Low Time tSKL fSCL = 400 kHz, CLOAD = 25 pF 1.3 — — µs Start Hold Time tSTH fSCL = 400 kHz, CLOAD = 25 pF 0.6 — — µs Start Setup Time tSTS fSCL = 400 kHz, CLOAD = 25 pF 0.6 — — µs Stop Setup Time tSPS fSCL = 400 kHz, CLOAD = 25 pF 0.6 — — µs Bus Free Time tBUF Between Stop and Start, fSCL = 400 kHz, CLOAD = 25 pF 1.3 — — µs SDA Setup Time tDS fSCL = 400 kHz, CLOAD = 25 pF 100 — — ns SDA Hold Time tDH fSCL = 400 kHz, CLOAD = 25 pF 100 — — ns SDA Valid Time tVD_DAT From SCL low to data valid, fSCL = 400 kHz, CLOAD = 25 pF — — 0.9 µs SDA ACK Valid Time tVD_ACK From SCL low to data valid, fSCL = 400 kHz, CLOAD = 25 pF — — 0.9 µs Suppressed Pulse Width (pulses up to and including this duration will be sup- pressed) tSPW fSCL = 400 kHz, CLOAD = 25 pF 50 — — ns Figure 5.1. I2C Interface Timing SCL D6 1/fSCL tSKH SDA tSKL tSTH D5 D4 D0 R/W ACK tDS tDH Start Bit Stop Bit tBUF tSTS tVD :ACK tSPS tSP EFP01 Energy Friendly PMIC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.3 | 43 |
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