8T33FS6111 datasheet(14/29 Pages) RENESAS

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LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL

FANOUT BUFFER

REVISION 1 12/02/14

8T33FS6111 DATA SHEET

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for

LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

The differential outputs are a low impedance follower output that

generate LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be

used for functionality. These outputs are designed to drive 50



transmission lines. Matched impedance techniques should be used

to maximize operating frequency and minimize signal distortion.



Figure 7A and Figure 7B show two different layouts which are

recommended only as guidelines. Other suitable clock layouts may

exist and it would be recommended that the board designers

simulate to guarantee compatibility across all printed circuit and clock

component process variations.

Figure 7A. 3.3V LVPECL Output Termination

Figure 7B. 3.3V LVPECL Output Termination



3.3V

125



125



o = 50

Input

3.3V

8T33FS6111 Datasheet(PDF) 14 Page - Renesas Technology Corp