8T33FS6111 datasheet(2/29 Pages) RENESAS

2 / 29 page

LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL

FANOUT BUFFER

REVISION 1 12/02/14

8T33FS6111 DATA SHEET

Pin Description and Characteristics

VCC

Power

Positive power supply. All VCC pins must be connected to the

positive power supply for correct DC and AC operation.

CLK_SEL

Input

Active clock input select.

CLKA

Input

LVPECL

Differential reference clock signal input.

nCLKA

Input

LVPECL

Differential reference clock signal input.

VBB

Output

Reference voltage output for single ended LVPECL operation.

CLKB

Input

HSTL/LVPECL

Alternative differential reference clock signal input.

nCLKB

Input

HSTL/LVPECL

Alternative differential reference clock signal input.

VEE

Power

Negative power supply.

VCC

Power

Positive power supply. All VCC pins must be connected to the

positive power supply for correct DC and AC operation.

nQ9

Output

LVPECL

Differential clock outputs.

Output

LVPECL

nQ8

Output

LVPECL

Differential clock outputs.

Output

LVPECL

nQ7

Output

LVPECL

Differential clock outputs.

Output

LVPECL

VCC

Power

Positive power supply. All VCC pins must be connected to the

positive power supply for correct DC and AC operation.

nQ6

Output

LVPECL

Differential clock outputs.

Output

LVPECL

nQ5

Output

LVPECL

Differential clock outputs.

Output

LVPECL

nQ4

Output

LVPECL

Differential clock outputs.

Output

LVPECL

nQ3

Output

LVPECL

Differential clock outputs.

Output

LVPECL

VCC

Power

Positive power supply. All VCC pins must be connected to the

positive power supply for correct DC and AC operation.

nQ2

Output

LVPECL

Differential clock outputs.

Output

LVPECL

nQ1

Output

LVPECL

Differential clock outputs.

Output

LVPECL

nQ0

Output

LVPECL

Differential clock outputs.

Output

LVPECL

VCC

Power

Positive power supply. All VCC pins must be connected to the

positive power supply for correct DC and AC operation.

Table 1. Pin Description

Number

Name

Type

Description

Table 2. Function Table

Control

Default

CLK_SEL

CLKA, nCLKA input pair is active. CLKA can

be driven by LVPECL compatible signals.

CLKB, nCLKB input pair is active.

CLKB can be driven by HSTL or LVPECL

compatible signals.

8T33FS6111 Datasheet(PDF) 2 Page - Renesas Technology Corp

8T33FS6111 Datasheet(HTML) 2 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Datasheet Download

Link URL