FUSB15201 datasheet(12/19 Pages) ONSEMI

12 / 19 page

FUSB15201

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Power and Sleep Behavior

The FUSB15201 has been optimized to conserve power

by utilizing peripheral interrupts and hardware autonomy.

The device can be configured via firmware to enter low

power states, disable unneeded peripherals and scale clock

frequencies based on different application needs.

The Type−C block is designed to function at the lowest

power states and will automatically wake when a Type−C

attach is detected. This minimizes total power consumption

when no device is attached.

Clock Sources

FUSB15201’s implements a dual oscillator architecture

to minimize power consumption.

• A 24 MHz internal RC oscillator to enable full

functionality.

• A 120 kHz internal RC oscillator that can be used for very

low power sleep modes.

TIMERS

32−bit General Purpose Timers (TIM0/1)

There are two 32−bit down−counters that generate

interrupts and status when the counter reaches 0. The timing

resolution depends on the programmable clock source and

pre−scale ratios.

32−bit Wake−up Timer (WUT)

The main purpose of the wakeup timer is to facilitate

scheduled exit from low power modes. It can also be used

for general purpose event timing.

32−bit Watchdog Timer (WDT)

The watchdog timer applies a reset to the system in the

event of a software failure, providing a way to recover

from software crashes. The watchdog timer is disabled

by default and must be enabled through software.

The watchdog is protected with a lock mechanism

to prevent rogue software from disabling the watchdog

functionality. A special value has to be written to the lock

clocked from the same oscillator as the core, which can be

LS_CLK or HS_CLK.

Serial Wire Debug Interface (SWD)

The Arm M0+ implementation includes a Debug Access

Port (DAP). The debug mode implementation includes

4 hardware breakpoints and 2 hardware watch points.

The Debug Access Port interface implementation is

the Arm Serial Wire Debug Port (SW−DAP) connected

to Pins SWCLK and SWDIO. The Serial Wire Debug Port

Interface uses a single bi−directional data connection. Each

operation consists of three phases: Packet request,

Acknowledge response, and Data transfer phase. Use any

Serial Wire Debug (SWD) compliant hardware debugger

interface to interact with the internals of the FUSB15201.

FUSB15201 Datasheet(PDF) 12 Page - ON Semiconductor

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