2 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB

2

REVISION D 04/22/15

9DBU0231 DATASHEET

Pin Configuration

SMBus Address Selection Table

Power Management Table

Power Connections

PLL Operating Mode

24 23 22 21 20 19

FB_DNC# 1

18 DIF1#

VDDR1.5 2

17 DIF1

CLK_IN 3

16 VDDA1.5

CLK_IN# 4

15 GNDA

GNDR 5

14 DIF0#

GNDDIG 6

13 DIF0

7

8

9 10 11 12

v prefix indicates internal 120KOhm pull down

resistor

24-pin VFQFPN, 4x4 mm, 0.5mm pitch

9DBU0231

epad is Gnd

^ prefix indicates internal 120KOhm pull up resistor

^v prefix indicates internal 120KOhm pull up AND

pull down resistor (biased to VDD/2)

Address

1101101

x

+

Read/Write bit

True O/P

Comp. O/P

0

X

X

X

Low

Low

Off

1

Running

0

X

Low

Low

On1

1

Running

1

0

Running

Running

On1

1

Running

1

1

Low

Low

On1

CLK_IN

OEx# Pin

PLL

DIFx

CKPWRGD_PD#

SMBus

OEx bit

1. If Bypass mode is selected, the PLL will be off, and outputs will be running.

VDD

GND

25

76

11,20

10,21

16

15

Note: epad on this device is not electrically connected to the die.

It should be connected to ground for best thermal performance.

Input receiver analog

Digital Power

DIF outputs

PLL Analog

Description

Pin Number

HiBW_BypM_LoBW#

MODE

Byte1 [7:6]

Readback

Byte1 [4:3]

Control

0

PLL Lo BW

00

00

MBypass

01

01

1

PLL Hi BW

11

11