M59DR032EA datasheet(5/43 Pages) STMICROELECTRONICS

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M59DR032EA, M59DR032EB

SUMMARY DESCRIPTION

The M59DR032E is a 32 Mbit (2Mbit x16) non-vol-

atile Flash memory that may be erased electrically

at block level and programmed in-system on a

Word-by-Word basis using a 1.65V to 2.2V VDD

supply for the circuitry and a 1.65V to 2.2V VDDQ

supply for the Input/Output pins. An optional 12V

VPP power supply is provided to speed up custom-

er programming.

The device features an asymmetrical block archi-

tecture. M59DR032E has an array of 71 blocks

and is divided into two banks, Banks A and B, pro-

viding Dual Bank operations. While programming

or erasing in Bank A, read operations are possible

in Bank B or vice versa. Only one bank at a time is

allowed to be in program or erase mode. The bank

architecture is summarized in Table 2, and the

Block Addresses are shown in Appendix A. The

Parameter Blocks are located at the top of the

memory address space for the M59DR032EA,

and at the bottom for the M59DR032EB.

Each block can be erased separately. Erase can

be suspended, in order to perform either read or

program in any other block, and then resumed.

Each block can be programmed and erased over

100,000 cycles.

Program and Erase commands are written to the

Command Interface of the memory. An internal

Program/Erase Controller takes care of the tim-

ings necessary for program and erase operations.

The end of a program or erase operation can be

detected and any error conditions identified in the

Status Register. The command set required to

control the memory is consistent with JEDEC stan-

dards.

The M59DR032E features an instant, individual

block locking scheme that allows any block to be

locked or unlocked with no latency, enabling in-

stant code and data protection. All blocks have two

levels of protection. They can be individually

locked and locked-down preventing any acciden-

tal programming or erasure. All blocks are locked

at Power Up and Reset.

The device includes a 128 bit Protection Register

and a Security Block to increase the protection of

a system’s design. The Protection Register is di-

vided into two 64 bit segments. The first segment

contains a unique device number written by ST,

while the second one is one-time-programmable

by the user. The user programmable segment can

be permanently protected. The Security Block, pa-

rameter block 0, can be permanently protected by

the user. Figure 4, shows the Security Block and

Protection Register Memory Map.

The device is available in TFBGA48 (7 x 12mm

and 7 x 7mm, 0.75mm pitch) packages and it is

supplied with all the bits erased (set to ‘1’).

Figure 2. Logic Diagram

Table 1. Signal Names

A0-A20

Address Inputs

DQ0-DQ15

Data Input/Outputs, Command Inputs

Chip Enable

Output Enable

Write Enable

Reset/Power-Down

Write Protect

VDD

Supply Voltage

VDDQ

Supply Voltage for Input/Output

Buffers

VPP

Optional Supply Voltage for

Fast Program & Erase

VSS

Ground

Not Connected Internally

AI06188

A0-A20

DQ0-DQ15

VDD

M59DR032EA

M59DR032EB

VSS

VDDQ VPP

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