Connection Diagrams

Dual-In-Line Package

TLF5599 – 2

Top View

Order Number MM58248N

See NS Package Number N40A

Plastic Chip Carrier

TLF5599 – 8

Top View

Order Number MM58248V

See NS Package Number V44A

FIGURE 2

Functional Description

This product is specifically designed to drive multiplexed or

non-multiplexed high voltage alphanumeric or dot matrix

vacuum fluorescent (VF) displays Character generation is

done externally in the microprocessor with a serial data

path to the display driver The MM58248 uses two signals

DATA IN and CLOCK with a format of a leading ‘1’ followed

by the 35 data bits hence allowing data transfer without an

additional signal A block diagram of the MM58248 is shown

in

Figure 1

Figure 2 shows the pinout of the MM58248 device where

output 1 (pin 18) is equivalent to bit 1 ie the first bit of data

to be loaded into the shift register following the start bit A

logic ‘1’ at the input will turn on the corresponding display

digitsegmentdot output

A significant reduction in discrete board components can be

achieved by the use of the MM58248 because external

pull-down resistors are not required Due to the nature of

the output stage both its on and off impedance values vary

as a function of the display voltage applied However

Fig-

ures 3a and 3b show that this output impedance will remain

constant for a fixed value of display voltage

Figure 4 demonstrates the critical timing requirements be-

tween CLOCK and DATA IN for the MM58248

In

Figure 5 a start bit of logic ‘1’ precedes the 35 bits of

data each bit being accepted on the rising edge of CLOCK

ie a ‘0’ – ‘1’ transition At the 36th clock a LOAD signal is

generated synchronously with the high state of the clock

thus loading the 35 bits of the shift register into the latches

At the low state of the clock a RESET signal is generated

clearing all bits of the shift register for the next set of data

Hence a complete set of 36 clock pulses is needed for the

MM58248 or the shift register will not clear To clear (reset)

the display driver at ‘power on’ or any time the following

flushing routine may be used Clock in 36 ‘‘zeroes’’ fol-

lowed by a ‘‘one’’ (start bit) followed by 35 ‘‘zeroes’’ This

procedure will completely blank the display It is recom-

mended to clear the driver at power on

Figure 6 shows a schematic diagram of a microprocessor-

based system where the MM58248 is used to provide the

anode drive for a 32-digit5x7dot matrix vacuum fluores-

cent (VF) display The grid drive in this example is provided

by another member of the high voltage display driver family

namely the MM58241 which has the additional features of

a BLANKING CONTROL pin a DATA OUT pin and an

ENABLE (external load signal) pin

3