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Preliminary Technical Data

Rev. PrA 15-Nov-04| Page 16 of 27

GENERAL DESCRIPTION

The AD5744/64 is a quad 14/16-bit, serial input, bipolar voltage

output DAC. It operates from supply voltages of ±11.4 V to

±16.5 V and has a buffered output voltage of up to ± 10.5 V.

Data is written to the AD5744/64 in a 24-bit word format, via a

3-wire serial interface. The device also offers an SDO pin, which

is available for daisy chaining or readback.

The AD5744/64 incorporates a power-on reset circuit, which

ensures that the DAC registers power up loaded with 0x0000.

The AD5744/64 also features a digital I/O port that may be

programmed via the serial interface, an analog temperature

sensor, on-chip 10 ppm/°C voltage reference, on-chip reference

buffers and per channel digital gain and offset registers.

DAC ARCHITECTURE

The DAC architecture of the AD5744/64 consists of a 14/16-bit

current-mode segmented R-2R DAC. The simplified circuit

diagram for the DAC section is shown in Figure 13.

The four MSBs of the 14/16-bit data word are decoded to drive

15 switches, E1 to E15. Each of these switches connects one of

the 15 matched resistors to either AGND or IOUT. The

remaining 12 bits of the data word drive switches S0 to S11 of

the 12-bit R-2R ladder network.

E15

Vref

E14

S11

S10

12 BIT R-2R LADDER

VOUT

AGND

R/8

4 MSBs DECODED INTO

15 EQUAL SEGMENTS

Figure 7. DAC Ladder Structure

REFERENCE BUFFERS

The AD5744/64 can operate with either an external or internal

reference. The reference inputs (REFAB and REFCD) have an

input range up to 5 V. This input voltage is then used to provide

a buffered positive and negative reference for the DAC cores.

The positive reference is given by

+ VREF = 2* VREF

While the negative reference to the DAC cores is given by

-VREF = -2*VREF

These positive and negative reference voltages (along with the

gain register values) define the output ranges of the DACs.

SERIAL INTERFACE

The AD5744/64 is controlled over a versatile 3-wire serial

interface that operates at clock rates of up to 30 MHz and is

compatible with SPI, QSPI, MICROWIRE and DSP standards.

Input Shift Register

The input shift register is 24 bits wide. Data is loaded into the

device MSB first as a 24-bit word under the control of a serial

clock input, SCLK. The input register consists of a read/write

bit, three register select bits, three DAC address bits and 14/16

data bits as shown in Table 8.The timing diagram for this

operation is shown in Figure 2.

Upon power-up the DAC registers are loaded with zero code

(0x0000). The corresponding output voltage depends on the

state of the BIN/2sCOMP pin. If the BIN/2sCOMP pin is tied to

DGND then the data coding is 2sComplement and the outputs

will power-up to 0V. If the BIN/2sCOMP pin is tied high then

the data coding is Offset binary and the outputs will power-up

to Negative Full-scale.

Standalone Operation

The serial interface works with both a continuous and noncon-

tinuous serial clock. A continuous SCLK source can only be

used if SYNC is held low for the correct number of clock cycles.

In gated clock mode, a burst clock containing the exact number

of clock cycles must be used and SYNC must be taken high after

the final clock to latch the data. The first falling edge of SYNC

starts the write cycle. Exactly 24 falling clock edges must be

applied to SCLK before SYNC is brought back high again; if

SYNC is brought high before the 24th falling SCLK edge, the

write is aborted. If more than 24 falling SCLK edges are applied

before SYNC is brought high, the input data will be corrupted.

The input register addressed is updated on the rising edge of

SYNC. In order for another serial transfer to take place, SYNC

must be brought low again. After the end of the serial data

transfer, data is automatically transferred from the input shift

When the data has been transferred into the input register of

the addressed DAC, all DAC registers and outputs can be

updated by taking LDAC low while SYNC is high.

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